Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode.

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.