Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.

Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall.

Abstract: Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.

Abstract: A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.

Abstract: A memory device, such as a ReRAM device includes plural interdigitated word lines and a single select transistor controlling plural vertical local bit lines. The interdigitated word lines may be word line combs containing word line fingers which are electrically connected using contact pads and a sidewall bridge interconnect. The select transistor may be a vertical TFT or a planar field effect transistor.

Abstract: A memory device, such as a ReRAM device includes plural interdigitated word lines and a single select transistor controlling plural vertical local bit lines. The interdigitated word lines may be word line combs containing word line fingers which are electrically connected using contact pads and a sidewall bridge interconnect. The select transistor may be a vertical TFT or a planar field effect transistor.

Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.

Abstract: A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source.

Abstract: An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.

Abstract: A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.

Abstract: An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.

Abstract: A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source.

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.

Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall.

Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.

Abstract: A manufacturing method of a semiconductor device is provided to improve the reliability of electrical coupling of the semiconductor device. The manufacturing method includes the steps of (a) laminating a main conductive film (base film) and a stopper insulating film (film to be measured) above the main conductive film, over a main surface of a semiconductor substrate, (b) forming an opening in the stopper film, (c) applying an electron beam (excitation beam) to the opening to emit characteristic X-rays, and (d) detecting the characteristic X-rays to determine the presence or absence, or thickness of the stopper insulating film at the bottom of the opening based on detection result of the characteristic X-rays. In the step (d), the presence or absence, or thickness of the stopper film is determined by a ratio of element components contained in the characteristic X-rays.