Abstract: Embodiments of the invention provide a memory allocation module that adopts memory-pool based allocation and is aware of the physical configuration of the memory blocks in order to manage the memory allocation intelligently while exploiting statistical characters of packet traffic. The memory-pool based allocation makes it easy to find empty memory blocks. Packet traffic characteristics are used to maximize the number of empty memory blocks.

Abstract: Embodiments of the invention provide a memory allocation module that adopts memory-pool based allocation and is aware of the physical configuration of the memory blocks in order to manage the memory allocation intelligently while exploiting statistical characters of packet traffic. The memory-pool based allocation makes it easy to find empty memory blocks. Packet traffic characteristics are used to maximize the number of empty memory blocks.

Abstract: A race logic circuit of the present invention includes: a WTA circuit for receiving an operand logic signal and outputting only a high signal which is the first to arrive among the operand logic signals; plural race lines for inputting the operand logic signal into the WTA circuit; a clock distribution line having plural delay devices connected in series, both ends of the respective delay devices being connected to a triggering line, the clock distribution line receiving an external clock and outputting a triggering signal into the triggering line; and plural operand logic signal input switches which are triggered by the triggering signal output from the triggering line, for deciding whether to input the operand logic signal into the race line. According to the race logic of the present invention makes it possible to compose various logic circuits. Especially, when realizing the race logic circuit as integrated circuits, time delay due to the transistors can be removed during the logic operation.

Abstract: A race logic circuit of the present invention includes: a WTA circuit for receiving an operand logic signal and outputting only a high signal which is the first to arrive among the operand logic signals; plural race lines for inputting the operand logic signal into the WTA circuit; a clock distribution line having plural delay devices connected in series, both ends of the respective delay devices being connected to a triggering line, the clock distribution line receiving an external clock and outputting a triggering signal into the triggering line; and plural operand logic signal input switches which are triggered by the triggering signal output from the triggering line, for deciding whether to input the operand logic signal into the race line. According to the race logic of the present invention makes it possible to compose various logic circuits. Especially, when realizing the race logic circuit as integrated circuits, time delay due to the transistors can be removed during the logic operation.