Patents by Inventor Semen P. Volfbeyn
Semen P. Volfbeyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10749541Abstract: A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.Type: GrantFiled: January 7, 2020Date of Patent: August 18, 2020Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn, Valeriy Serebryanskiy
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Patent number: 10355706Abstract: A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. hm(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eqm are determined from Eqm(F)=T(F)/hm(F), to form equalizing frequency responses. Sets of equalizing coefficients Cm(p) pursuant to discrete Fourier transforms on Eqm(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients Cm(p).Type: GrantFiled: November 28, 2018Date of Patent: July 16, 2019Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn, Alexander Taratorin, Valeriy Serebryanskiy
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Patent number: 10305707Abstract: A digital down-converter with baseband equalization comprises a composite analog-to-digital converter (ADC) adapted to convert an applied RF analog signal to be processed to a digital signal, and then down-convert the digital signal to a baseband frequency region, and then perform equalization on the down-converted digital signal, thereby reducing distortions caused by introduction of spurious signals by the ADC.Type: GrantFiled: April 23, 2018Date of Patent: May 28, 2019Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn, Alexander Taratorin
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Patent number: 9933467Abstract: Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave fLF, (ii) sine wave harmonics at a high frequency fHF, (iii) L pairs of sideband components at frequencies k·fHF±2·fLF, where k odd, and M pairs of sideband components at frequencies k·fHF±fLF, where k is even. At DUT output, (i) phase ?LF at frequency fLF is measured, (ii) both sideband phase ?right(k) at frequencies k·fHF+2·fLF and phase ?left(k) at frequencies k·fHF?2·fLF for odd k, are measured, and (iii) both sideband phases ?right(k) at frequencies k·fHF+fLF and ?left(k) at frequencies k·fHF?fLF for even k, are measured. Group delay ?k at frequencies k·FHF, are determined from: ?k=(?right(k)??left(k)?4·?L)/(4·fLF) for k odd, and ?k=(?right(k)??left(k)?2·?L)/(2·fLF) for k even.Type: GrantFiled: September 16, 2016Date of Patent: April 3, 2018Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Alexander Taratorin, Semen P. Volfbeyn
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Publication number: 20180080965Abstract: Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave fLF, (ii) sine wave harmonics at a high frequency fHF, (iii) L pairs of sideband components at frequencies k·fHF±2·fLF, where k odd, and M pairs of sideband components at frequencies k·fHF±fLF, where k is even. At DUT output, (i) phase ?LF at frequency fLF is measured, (ii) both sideband phase ?right(k) at frequencies k·fHF+2·fLF and phase ?left(k) at frequencies k·fHF?2·fLF for odd k, are measured, and (iii) both sideband phases ?right(k) at frequencies k·fHF+fLF and ?left(k) at frequencies k·fHF?fLF for even k, are measured. Group delay ?k at frequencies k·FHF, are determined from: ?k=(?right(k)??left(k)?4·?L)/(4·fLF) for k odd, and ?k=(?right(k)??left(k)?2·?L)/(2·fLF) for k even.Type: ApplicationFiled: September 16, 2016Publication date: March 22, 2018Applicant: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Alexander Taratorin, Semen P. Volfbeyn
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Publication number: 20170141786Abstract: A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.Type: ApplicationFiled: August 5, 2016Publication date: May 18, 2017Applicant: Guzik Technical EnterprisesInventors: Semen P. Volfbeyn, Anatoli B. Stein, Alexander Taratorin
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Patent number: 9641191Abstract: A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.Type: GrantFiled: August 5, 2016Date of Patent: May 2, 2017Assignee: Guzik Technical EnterprisesInventors: Semen P. Volfbeyn, Anatoli B. Stein, Alexander Taratorin
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Patent number: 9634679Abstract: A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.Type: GrantFiled: August 19, 2016Date of Patent: April 25, 2017Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn, Alexander Taratorin, Igor Tarnikov, Valeriy Serebryanskiy
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Patent number: 9344301Abstract: An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory.Type: GrantFiled: May 29, 2015Date of Patent: May 17, 2016Assignee: Guzik Technical EnterprisesInventors: Nahum Guzik, Anatoli B. Stein, Semen P. Volfbeyn, Igor Tarnikov
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Publication number: 20150349983Abstract: An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory.Type: ApplicationFiled: May 29, 2015Publication date: December 3, 2015Applicant: GUZIK TECHNICAL ENTERPRISESInventors: Nahum Guzik, Anatoli B. Stein, Semen P. Volfbeyn, Igor Tarnikov
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Patent number: 9172388Abstract: An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input.Type: GrantFiled: June 10, 2015Date of Patent: October 27, 2015Assignee: GUZIK TECHNICAL ENTERPRISESInventors: Anatoli B. Stein, Semen P. Volfbeyn
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Patent number: 9148162Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.Type: GrantFiled: January 13, 2015Date of Patent: September 29, 2015Assignee: GUZIK TECHNICAL ENTERPRISESInventors: Anatoli B. Stein, Semen P. Volfbeyn
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Publication number: 20150200679Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.Type: ApplicationFiled: January 13, 2015Publication date: July 16, 2015Applicant: GUZIK TECHNICAL ENTERPRISESInventors: Anatoli B. Stein, Semen P. Volfbeyn
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Patent number: 8542142Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.Type: GrantFiled: February 21, 2013Date of Patent: September 24, 2013Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn, Valeriy Serebryanskiy
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Patent number: 8537044Abstract: An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer.Type: GrantFiled: December 28, 2012Date of Patent: September 17, 2013Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn
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Patent number: 8477445Abstract: A write clock generator for use in writing data to a rotating patterned magnetic media disk is disclosed. The generator includes a magnetic read head for generating a succession of servo signals representative of succession of servo magnetization patterns detected from a corresponding succession of arcuate sectors along a circular data track on the disk. A preamble processor generates a corresponding succession of sector pair signals representative of the lengths of adjacent sectors along the data track on a rolling pair-wise basis. A next sector length predictor processor determines for a succession of pairs of sectors, a length ratio of the lengths of the sectors in the respective pairs of sectors.Type: GrantFiled: December 5, 2012Date of Patent: July 2, 2013Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn
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Patent number: 7408495Abstract: Time variant interleaving equalization of an interleaved analog to digital converter is disclosed. A high-frequency analog input signal is converted into a plurality of individual digital signals using a plurality of interleaved analog-to-digital converters. the plurality of individual digital signals are interleaved into a composite digital signal. The composite digital signal is processed in a time variant interleaving equalizer using a plurality of sets of equalizer coefficients.Type: GrantFiled: July 25, 2006Date of Patent: August 5, 2008Assignee: Guzik Technical EnterprisesInventors: Anatoli Stein, Semen P. Volfbeyn
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Publication number: 20070262895Abstract: Time variant interleaving equalization of an interleaved analog to digital converter is disclosed. A high-frequency analog input signal is converted into a plurality of individual digital signals using a plurality of interleaved analog-to-digital converters. the plurality of individual digital signals are interleaved into a composite digital signal. The composite digital signal is processed in a time variant interleaving equalizer using a plurality of sets of equalizer coefficients.Type: ApplicationFiled: July 25, 2006Publication date: November 15, 2007Inventors: Anatoli Stein, Semen P. Volfbeyn
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Patent number: 7245449Abstract: Analysis of a read back signal in a magnetic recording device is disclosed. The read back signal is converted to a digital read back signal, and a low frequency component of the digital read back signal is restored. A sample clock is recovered from the restored digital read back signal, and the restored digital read back signal is averaged using the recovered sample clock. A timing error is calculated based at least in part on the averaged restored digital read back signal.Type: GrantFiled: October 11, 2005Date of Patent: July 17, 2007Assignee: Guzik Technical EnterprisesInventors: Anatoli Stein, Semen P. Volfbeyn, Vladislav A. Klimov, Igor Tarnikov
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Patent number: 7165211Abstract: A decoder for detecting data within an input signal with attenuated low frequency components that comprises a Viterbi decoder, is disclosed. Viterbi decoder internal data is used along with its output bits to reduce delay between the restored direct current (DC) component and the input signal to zero. As a result, increased accuracy of DC restoration and corresponding bit error rate reduction are achieved.Type: GrantFiled: September 20, 2004Date of Patent: January 16, 2007Assignee: Guzik Technical EnterprisesInventors: Anatoli B. Stein, Semen P. Volfbeyn