Abstract: An electronics package comprises an integrated circuit (IC) coupled to an IC substrate in a flip-chip ball grid array (FCBGA) configuration. The IC comprises a high density pattern of interconnect pads around its periphery for coupling to a corresponding pattern of bonding pads on the IC substrate. The substrate bonding pads are uniquely arranged to accommodate a high density of interconnect pads on the IC while taking into account various geometrical constraints on the substrate, such as bonding pad size, trace width, and trace spacing. In one embodiment, the substrate bonding pads are arranged in a zigzag pattern. In a further embodiment, the technique is used for bonding pads on a printed circuit board to which an IC package is coupled. Methods of fabrication, as well as application of the package to an electronic package, an electronic system, and a data processing system, are also described.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: An electronics package comprises an integrated circuit (IC) coupled to an IC substrate in a flip-chip ball grid array (FCBGA) configuration. The IC comprises a high density pattern of interconnect pads around its periphery for coupling to a corresponding pattern of bonding pads on the IC substrate. The substrate bonding pads are uniquely arranged to accommodate a high density of interconnect pads on the IC while taking into account various geometrical constraints on the substrate, such as bonding pad size, trace width, and trace spacing. In one embodiment, the substrate bonding pads are arranged in a zigzag pattern. In a further embodiment, the technique is used for bonding pads on a printed circuit board to which an IC package is coupled. Methods of fabrication, as well as application of the package to an electronic package, an electronic system, and a data processing system, are also described.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.