Patents by Inventor Seng Kiong Teng
Seng Kiong Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9177834Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.Type: GrantFiled: February 19, 2014Date of Patent: November 3, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Meng Kong Lye, Lan Chu Tan, Seng Kiong Teng
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Patent number: 9129951Abstract: A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire.Type: GrantFiled: October 17, 2013Date of Patent: September 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Seng Kiong Teng, Ly Hoon Khoo, Wen Shi Koh
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Publication number: 20150235924Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Inventors: Chee Seng Foong, Meng Kong Lye, Lan Chu Tan, Seng Kiong Teng
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Publication number: 20150118802Abstract: A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates.Type: ApplicationFiled: August 21, 2014Publication date: April 30, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Boon Yew Low, Teck Beng Lau, Seng Kiong Teng, Shufeng Zhao
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Publication number: 20150108623Abstract: A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Inventors: Seng Kiong Teng, Ly Hoon Khoo, Wen Shi Koh
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Patent number: 8987881Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.Type: GrantFiled: July 10, 2013Date of Patent: March 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Seng Kiong Teng, Ly Hoon Khoo, Navas Khan Oratti Kalandar
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Publication number: 20150014834Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.Type: ApplicationFiled: July 10, 2013Publication date: January 15, 2015Inventors: Seng Kiong Teng, Ly Hoon Khoo, Navas Khan Oratti Kalandar
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Patent number: 8933547Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.Type: GrantFiled: November 21, 2013Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
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Patent number: 8012799Abstract: A method for packaging a semiconductor die or assembling a semiconductor device that includes a heat spreader begins with attaching the heat spreader to a film and dispensing a mold compound in granular form onto the film such that the mold compound at least partially covers the film and the heat spreader. The film with the attached heat spreader is placed in a first mold section. A substrate having a semiconductor die attached and electrically coupled to it are placed in a second mold section and then the first and second mold sections are mated such that the die is covered by the heat spreader. The granular mold compound is then melted so that the mold compound covers the die and sides of the heat spreader. The first and second mold sections then are separated. The film, which adheres to the substrate, is removed to expose a top surface of the heat spreader, and thus a semiconductor device is formed.Type: GrantFiled: June 8, 2010Date of Patent: September 6, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Ruzaini Ibrahim, Seng Kiong Teng
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Publication number: 20110204498Abstract: A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length.Type: ApplicationFiled: February 24, 2010Publication date: August 25, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Yin Kheng Au, Mohd Rusli Ibrahim, Meng Kong Lye, Zi Song Poh, Seng Kiong Teng, Kesyakumar V.C. Muniandy