Abstract: Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.

Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.

Abstract: An integrated circuit may include multiple circuit blocks, each with an associated latency value. As an example, transceiver circuitry in an integrated circuit may receive different data packets and circuit blocks in the transceiver circuitry may have different latency values depending on the data packets received. The integrated circuit may further include latency computation circuitry that receives the different latency values from the multiple circuit blocks. The latency computation circuitry may accordingly output a total latency value for the multiple circuit blocks in the integrated circuit based on the received latency values.

Abstract: Integrated circuits with dynamic pin routing capabilities are provided. An integrated circuit may include circuitry under test and a dynamic signal routing controller. The dynamic signal routing controller may include multiplexers, a test register, and a signal select register. The circuitry under test may be connected to internal test lines that receive static test signals and dynamic test signals. The internal test lines that receive static test signals may be selectively routed to the test register (e.g., test registers store static test signals) while the internal test lines that receive dynamic test signals may be selectively routed to test pins (e.g., dynamic test signals are driven through the test pins). Each multiplexer may have a given input that is connected to the test register and additional inputs that are connected to the test pins. The signal select register stores control bits that configure the routing performed by each multiplexer.