Patents by Inventor Senthil Sundaramoorthy

Senthil Sundaramoorthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performance and area scalable cell architecture technology
    Patent number: 7564077
    Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: July 21, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
  • Performance and Area Scalable Cell Architecture Technology
    Publication number: 20070290270
    Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
    Type: Application
    Filed: May 7, 2007
    Publication date: December 20, 2007
    Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone