Patents by Inventor Senthilkannan Chandrasekaran

Senthilkannan Chandrasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER AND THROUGHPUT OPTIMIZATION OF AN UNBALANCED INSTRUCTION PIPELINE
    Publication number: 20160011642
    Abstract: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.
    Type: Application
    Filed: September 21, 2015
    Publication date: January 14, 2016
    Inventor: Senthilkannan Chandrasekaran
  • Different clock frequencies and stalls for unbalanced pipeline execution logics
    Patent number: 9141392
    Abstract: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Senthilkannan Chandrasekaran
  • Systems and method for spur supression in a multiple radio SoC
    Patent number: 8750805
    Abstract: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vivek Singhal, Senthilkannan Chandrasekaran, Sumanth Poddutur, Jasbir Singh
  • SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC
    Publication number: 20120154010
    Abstract: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Vivek Singhal, Senthilkannan Chandrasekaran, Sumanth Poddutur, Jasbir Singh
  • POWER AND THROUGHPUT OPTIMIZATION OF AN UNBALANCED INSTRUCTION PIPELINE
    Publication number: 20110258417
    Abstract: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 20, 2011
    Inventor: Senthilkannan Chandrasekaran