Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.

Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract: A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.