Abstract: An analog-to-digital converter (ADC) includes first and second circuits, a differential amplifier, a comparator and a digital-to-analog converter (DAC). The first circuit samples a reset voltage, amplifies the sampled reset voltage, and subtracts a first reference voltage from the amplified reset voltage to produce a first difference. The second circuit samples a signal voltage, amplifies the sampled signal voltage, and subtracts a second reference voltage from the amplified signal voltage to produce a second difference. The differential amplifier produces a third difference based a comparison of the first and second differences from the first and second circuits. The comparator compares an output of the differential amplifier with at least one predetermined comparison voltage and outputs a comparison result as a digital value. The DAC is connected to the first and second circuits and the comparator, and controls the first and second reference voltages in response to the digital value.

Abstract: The invention is directed generally to a correlated double-sampling (CDS) circuit using a smaller number of capacitors than conventional circuits. In embodiments of the invention, a first portion of the CDS circuit uses just two capacitors to sample the reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage. A second portion of the CDS circuit uses just two capacitors to sample the signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage. Embodiments of the invention also provide a cyclic analog-to-digital converter (ADC) including the CDS circuit.