Abstract: A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern.

Abstract: The present invention is directed to a capacitor having a reaction preventing layer and a method forming the same. A lower electrode of silicon is formed on a substrate. An assistance layer of metal oxide or metal nitride is formed on the lower electrode. A nitridation process is performed to enable the silicon of the lower electrode, the assistance layer, and nitrogen supplied by the nitridation process to react with one another, forming a reaction preventing layer comprising metal silicon oxynitride or metal silicon nitride. A high-k dielectric film and an upper electrode are formed on the reaction preventing layer.

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.

Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.

Abstract: Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract: A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps.

Abstract: A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.

Abstract: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.

Abstract: A method of manufacturing a memory device that improves electrical characteristics of an MIM capacitor using a zirconium oxide film (ZrO2) as a dielectric film includes: forming a lower metal electrode on a semiconductor substrate; forming a two or more-layered dielectric film including zirconium oxide films on the lower metal electrode; forming an upper metal electrode on the dielectric film; forming an MIM capacitor by patterning the upper metal electrode, the dielectric film, and the lower metal electrode; forming an interlayer insulating film covering the MIM capacitor; forming contacts in the insulating film; and performing heat treatment at a temperature range of 425 to 500° C.

Abstract: A method of forming a metallic oxide film using atomic layer deposition includes loading a substrate into a reactor, supplying a metallic source gas into the reactor and absorbing the metallic source gas onto the substrate, purging the remaining metallic source gas that does not react, with the substrate, and directly producing plasma of an N-group-containing oxide reactant gas in the reactor.

Abstract: In a method and an apparatus for forming metal oxide on a substrate, a source gas including metal precursor flows along a surface of the substrate to form a metal precursor layer on the substrate. An oxidizing gas including ozone flows along a surface of the metal precursor layer to oxidize the metal precursor layer so that the metal oxide is formed on the substrate. A radio frequency power is applied to the oxidizing gas flowing along the surface of the metal precursor layer to accelerate a reaction between the metal precursor layer and the oxidizing gas. Acceleration of the oxidation reaction may improve electrical characteristics and uniformity of the metal oxide.

Abstract: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.

Abstract: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.

Abstract: In a method of fabricating a capacitor, an interlayer insulating layer is formed on a semiconductor substrate. A contact plug penetrating the interlayer insulating layer is formed. An oxidation barrier layer and a molding layer are sequentially formed on the semiconductor substrate having the contact plug and the interlayer insulating layer. The molding layer is patterned to form a first lower electrode contact hole which exposes the oxidation barrier layer on the contact plug. An electrode layer pattern covering an inner sidewall of the first lower electrode contact hole is formed. The oxidation barrier layer exposed by the electrode layer pattern is etched to form a second lower electrode contact hole which exposes the contact plug. A conductive layer pattern covering an inner wall of the second lower electrode contact hole is then formed.

Abstract: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.

Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.

Abstract: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.

Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.