Abstract: A method of balancing a plurality of battery cells includes acquiring an open circuit voltage (OCV) of a battery cell of the plurality of battery cells connected in series; determining a state of charge (SOC) of the battery cell based on the OCV of the battery cell; determining a differential value in the OCV of the battery cell per a change of the SOC of the battery cell, in accordance with the SOC of the battery cell; and activating cell balancing of the plurality of battery cells when the differential value is greater than a reference value.

Abstract: A display apparatus is provided. The display apparatus includes a motion recognition device configured to recognize a user motion, a display device configured to display an image on a screen; an application execution device configured to execute at least one portion of a service, and a controller configured to control the display device to capture the displayed image and display at least one service item which is related to the captured image with the captured image on the screen in response to the user motion being recognized, and control the application execution device to execute the at least one portion of the service which corresponds to a selected service item selected by the user motion.

Abstract: A method of balancing a plurality of battery cells includes acquiring an open circuit voltage (OCV) of a battery cell of the plurality of battery cells connected in series; determining a state of charge (SOC) of the battery cell based on the OCV of the battery cell; determining a differential value in the OCV of the battery cell per a change of the SOC of the battery cell, in accordance with the SOC of the battery cell; and activating cell balancing of the plurality of battery cells when the differential value is greater than a reference value.

Abstract: A broadcasting receiving apparatus includes: a signal receiving unit which receives a first signal and a second signal different from the first signal; a signal processing unit which processes the first and second signals; a communication unit which communicates with an external device to output a sound; and a controller which controls the signal processing unit and the communication unit to process a video signal of the first signal to be displayed and to process an audio signal of the second signal to be transmitted to the external device if the first signals contains the video signal and the second signal contains only the audio signal.

Abstract: A broadcasting receiving apparatus includes: a signal receiving unit which receives a first signal and a second signal different from the first signal; a signal processing unit which processes the first and second signals; a communication unit which communicates with an external device to output a sound; and a controller which controls the signal processing unit and the communication unit to process a video signal of the first signal to be displayed and to process an audio signal of the second signal to be transmitted to the external device if the first signals contains the video signal and the second signal contains only the audio signal.

Abstract: A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.

Abstract: An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.

Abstract: A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.

Abstract: An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.