Patents by Inventor Seon Hee Moon
Seon Hee Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980632Abstract: Disclosed is fucosyllactose having antiviral activity and inhibitory activity against viral infection, and a method for preventing or treating a viral infection by administering a composition including fucosyllactose as an active ingredient to a subject in need thereof. It was found that 2?-fucosyllactose and 3-fucosyllactose, which are human milk oligosaccharides (HMOs), have antiviral activity, and in particular, 3-fucosyllactose in vitro and in vivo exhibits much higher antiviral activity and inhibitory activity against viral infection compared to 2?-fucosyllactose and is thus useful as an antiviral agent.Type: GrantFiled: November 23, 2022Date of Patent: May 14, 2024Assignee: ADVANCED PROTEIN TECHNOLOGIES CORP.Inventors: Dae Hyuk Kweon, Seok Oh Moon, Jung Hee Moon, Chul Soo Shin, Jong Won Yoon, Seon Min Jeon, Young Ha Song, Jong Gil Yoo
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Publication number: 20240141206Abstract: Disclosed are an adhesive film and a display member including the same. The adhesive film includes a matrix including a (meth)acrylic copolymer containing hydroxyl group and nanoparticles dispersed in the matrix, wherein a difference in cohesive energy between the matrix and the nanoparticles is about 20,000 J/mol or less.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Seon Hee SHIN, Hyung Rang MOON, Il Jin KIM
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Patent number: 11515265Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.Type: GrantFiled: July 21, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seon Hee Moon, Myung Sam Kang, Jin Gu Kim
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Patent number: 11075193Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.Type: GrantFiled: May 21, 2019Date of Patent: July 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Sam Kang, Young Gwan Ko, Yong Jin Park, Seon Hee Moon
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Publication number: 20200350262Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee Moon, Myung Sam Kang, Jin Gu Kim
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Patent number: 10748856Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.Type: GrantFiled: August 14, 2018Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee Moon, Myung Sam Kang, Jin Gu Kim
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Patent number: 10727212Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.Type: GrantFiled: October 25, 2018Date of Patent: July 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee Moon, Myung Sam Kang, Young Gwan Ko, Chang Bae Lee, Jin Su Kim
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Publication number: 20200144235Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.Type: ApplicationFiled: May 21, 2019Publication date: May 7, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Sam Kang, Young Gwan Ko, Yong Jin Park, Seon Hee Moon
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Publication number: 20190287953Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.Type: ApplicationFiled: October 25, 2018Publication date: September 19, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee MOON, Myung Sam KANG, Young Gwan KO, Chang Bae LEE, Jin Su KIM
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Publication number: 20190287924Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.Type: ApplicationFiled: August 14, 2018Publication date: September 19, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee MOON, Myung Sam KANG, Jin Gu KIM
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Patent number: 9345142Abstract: There are provided a chip embedded board and a method of manufacturing the same. The chip embedded board includes: a core substrate; a first build-up layer formed on one surface of the core substrate and having a cavity formed therein; a chip disposed in the cavity; and an insulating layer filled in the cavity in which the chip is disposed, wherein one surface of the chip is positioned in a circuit layer positioned at the outermost layer of the first build-up layer.Type: GrantFiled: November 11, 2014Date of Patent: May 17, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seon Hee Moon, Young Do Kweon, Jeong Ho Lee
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Patent number: 9196506Abstract: A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer.Type: GrantFiled: October 1, 2012Date of Patent: November 24, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung Jin Jeon, Jong In Ryu, Seung Wan Shin, Seon Hee Moon, Young Do Kweon, Seung Wook Park
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Publication number: 20150138741Abstract: There are provided a chip embedded board and a method of manufacturing the same. The chip embedded board includes: a core substrate; a first build-up layer formed on one surface of the core substrate and having a cavity formed therein; a chip disposed in the cavity; and an insulating layer filled in the cavity in which the chip is disposed, wherein one surface of the chip is positioned in a circuit layer positioned at the outermost layer of the first build-up layer.Type: ApplicationFiled: November 11, 2014Publication date: May 21, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seon Hee Moon, Young Do Kweon, Jeong Ho Lee
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Publication number: 20150083480Abstract: Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern.Type: ApplicationFiled: December 30, 2013Publication date: March 26, 2015Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Seon Hee MOON, Seung Wook Park, Chang Bae Lee
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Publication number: 20140251657Abstract: Embodiments of the invention provide a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Jin JEON, Young Do KWEON, Seung Wook PARK, Seon Hee MOON
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Patent number: 8756804Abstract: Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.Type: GrantFiled: August 19, 2011Date of Patent: June 24, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung Jin Jeon, Young Do Kweon, Seung Wook Park, Seon Hee Moon
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Patent number: 8624128Abstract: A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.Type: GrantFiled: September 16, 2011Date of Patent: January 7, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Ju-Pyo Hong, Young-Do Kweon, Jin-Gu Kim, Seon-Hee Moon, Dong-Jin Lee, Seung-Wook Park
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Patent number: 8273660Abstract: A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.Type: GrantFiled: February 3, 2011Date of Patent: September 25, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Jingli Yuan, Seon Hee Moon, Ju Pyo Hong, Jae Kwang Lee
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Publication number: 20120161323Abstract: Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a photosensitive insulating layer formed on one surface of the base substrate and having a roughness formed on a surface thereof; and a seed layer formed on one surface of the photosensitive insulating layer.Type: ApplicationFiled: March 4, 2011Publication date: June 28, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yoon Su KIM, Seon Hee MOON, Seung Wan SHIN, Young Do KWEON
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Publication number: 20120073870Abstract: Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.Type: ApplicationFiled: August 19, 2011Publication date: March 29, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Jin JEON, Young Do KWEON, Seung Wook PARK, Seon Hee MOON