Patents by Inventor Seong-Goo Kim
Seong-Goo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12066185Abstract: According to an embodiment, a monitoring device, comprising: a sensor for sensing inflow gas information including a component and a concentration of an inflow gas introduced into a regenerative thermal oxidizer (RTO); and a processor for determining residual gas information including a component and a concentration of a residual gas in the RTO by using the inflow gas information, and updating an inflow amount per unit time of the inflow gas according to a risk level of the RTO determined based on the residual gas information, is provided.Type: GrantFiled: December 10, 2020Date of Patent: August 20, 2024Assignee: TAESUNG ENVIRONMENTAL RESEARCH INSTITUTE CO., LTD.Inventors: Gi Yeol Yun, Seok Man Kim, Nam Goo Moon, Seong Hee Kang
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Publication number: 20240262674Abstract: A cold water tank for a direct water purifier is provided.Type: ApplicationFiled: February 8, 2022Publication date: August 8, 2024Applicant: COWAY CO., LTD.Inventors: Hee Joo KANG, Hee Do JUNG, Chan Jung PARK, Jong Hwan LEE, Hyun Kang LEE, Hyun Goo KIM, Yoo Won OH, Da Woon JUNG, Min Chul YONG, Dong Min OH, Seong Min PARK
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Publication number: 20240123485Abstract: Disclosed is a processing apparatus for rounding an edge of a lead tab for a secondary battery, comprising: a loading unit on which the lead tab manufactured by the lead tab manufacturing apparatus is loaded and seated; a primary edge processing unit installed at a downstream side of the loading unit; a secondary edge processing unit installed at a downstream side of the primary edge processing unit; an unloading unit installed at a downstream side of the secondary edge processing unit and configured to load the lead tab transferred from the secondary edge processing unit and discharge the loaded lead tab to the outside; and a transfer unit configured to load the lead tab.Type: ApplicationFiled: May 18, 2022Publication date: April 18, 2024Inventors: Ji-Ho KIM, Hoon Hee LEE, Seong Goo KIM
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Patent number: 8482045Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.Type: GrantFiled: July 16, 2012Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
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Patent number: 8378497Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.Type: GrantFiled: April 13, 2010Date of Patent: February 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Goo Kim, Hyeong-Sun Hong, Dong-Hyun Kim, Nam-Jung Kang
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Publication number: 20120273898Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.Type: ApplicationFiled: July 16, 2012Publication date: November 1, 2012Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
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Patent number: 8293604Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: GrantFiled: July 19, 2010Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Patent number: 8283714Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.Type: GrantFiled: April 13, 2011Date of Patent: October 9, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
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Patent number: 8174065Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.Type: GrantFiled: July 21, 2010Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
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Patent number: 8164119Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.Type: GrantFiled: January 27, 2011Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-Won Seo, Byung-Hyug Roh, Seong-Goo Kim, Sang-Min Jeon
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Patent number: 8039896Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.Type: GrantFiled: May 9, 2008Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
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Patent number: 8022457Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.Type: GrantFiled: November 16, 2006Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
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Publication number: 20110186923Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
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Publication number: 20110147800Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.Type: ApplicationFiled: January 27, 2011Publication date: June 23, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeoung-Won SEO, Byung-Hyug ROH, Seong-Goo Kim, Sang-Min Jeon
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Patent number: 7952129Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.Type: GrantFiled: June 11, 2010Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim
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Patent number: 7888720Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.Type: GrantFiled: October 2, 2007Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-Won Seo, Byung-Hyug Roh, Seong-Goo Kim, Sang-Min Jeon
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Publication number: 20100283094Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.Type: ApplicationFiled: July 21, 2010Publication date: November 11, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
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Publication number: 20100285645Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.Type: ApplicationFiled: July 19, 2010Publication date: November 11, 2010Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
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Publication number: 20100244124Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.Type: ApplicationFiled: June 11, 2010Publication date: September 30, 2010Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim
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Patent number: 7781285Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.Type: GrantFiled: June 9, 2006Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo