Abstract: There is provided a cooperative driving control method based on a vehicle security status. The cooperative driving method according to an embodiment includes: identifying a security status of a cooperative driving target vehicle; determining a cooperative driving strategy according to the identified security status; and controlling driving according to the determined cooperative driving strategy. Accordingly, cooperative driving may be performed or excluded based on a security status of a target vehicle, so that an accident may be prevented from being caused by cooperative driving with a problematic vehicle, and safety of a driver and an occupant may be guaranteed.

Abstract: An electric-axle device for a commercial vehicle that can minimize the frequency of using a main brake when braking, may include a first clutch device disposed between a motor and a differential casing to transmit or block power, a second clutch device disposed between the differential casing and a disc, an electromagnetic brake applying a braking force to the disc, and that can increase a coasting distance and improve energy efficiency and durability of the motor by disengaging the first clutch device and the second clutch device such that kinetic energy, which is transmitted to the motor from an axle shaft, is blocked as if a neutral gear of a transmission is engaged, when the vehicle coasts.

Abstract: A wafer level package includes: a substrate; an element portion disposed on one surface of the substrate; a cap disposed on the substrate to cover the element portion; a connection portion electrically connected to the element portion; and a bonding portion disposed on an outer side of the connection portion, wherein the bonding portion is disposed on a first surface of one of the substrate and the cap, wherein one end portion of the connection portion is disposed on a second surface having a step difference from the first surface, and wherein the connection portion and the bonding portion are formed of a eutectic material.

Abstract: A non-volatile memory device including a substrate including a first area and a second area, a mold structure on the substrate, the mold structure including gate electrodes and mold insulating films alternately stacked on each other in a stepwise manner, an interlayer insulating film covering the mold structure, a channel structure on the first area, the channel structure extending through the mold structure and connected to the gate electrodes, and a through-contact on the second area and extending through the interlayer insulating film, the through-contact including a first portion in a first trench and a second portion in a second trench, the first portion including a liner film along a sidewall and a bottom surface of the first trench and a filling film on the liner film, wherein the filling film being a multi-grain conductive material, and the second portion being a single grain conductive material, may be provided.

Abstract: A communication apparatus is provided to include an apparatus enclosure that includes a substrate seating surface and at least one or more connection grooves formed on the substrate seating surface, a first printed circuit board disposed on the substrate seating surface, a second printed circuit board disposed on the substrate seating surface on one side of the first printed circuit board, and at least one or more connectors disposed within the connection groove and configured to electrically connect the first printed circuit board and the second printed circuit board.

Abstract: The present disclosure relates to an electronic device, and more specifically, to an electronic device including a printed circuit board including a heat-generating element arranged on one surface thereof, and a heat transfer coin provided such that one surface of the heat transfer coin comes into contact with a portion of the other surface of the printed circuit board, opposite to the heat-generating element, so as to dissipate heat generated from the heat-generating element. Accordingly, the present disclosure provides an advantage of improving heat dissipation performance without increasing the thickness of the printed circuit board.

Abstract: The present invention relates to a signal shielding apparatus and an antenna apparatus including same, and in particular, comprises a shield cover which is stacked and disposed on a printed board assembly (hereinafter, abbreviated to “PBA”), in which a plurality of signal-related components are mounted on one side thereof to prevent leakage of a signal from the plurality of signal-related components, wherein a grooved shield cover seating groove is formed in one surface of the PBA, and an insertion end insertably seated in the shield cover seating groove is integrally formed in the other surface from among one surface and the other surface of the shield cover, the other surface facing the one surface of the PBA, thereby providing advantages in that an increase in the manufacturing cost may be prevented, EMI shielding may be facilitated, and heat dissipation performance may be significantly improved.

Abstract: An electric-axle device for a commercial vehicle that can minimize the frequency of using a main brake when braking, may include a first clutch device disposed between a motor and a differential casing to transmit or block power, a second clutch device disposed between the differential casing and a disc, an electromagnetic brake applying a braking force to the disc, and that can increase a coasting distance and improve energy efficiency and durability of the motor by disengaging the first clutch device and the second clutch device such that kinetic energy, which is transmitted to the motor from an axle shaft, is blocked as if a neutral gear of a transmission is engaged, when the vehicle coasts.

Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

Abstract: A method of forming a tungsten film including disposing a substrate inside a process chamber; performing a tungsten nucleation layer forming operation for forming a tungsten nucleation layer on the substrate, performing a first operation for forming a portion of a tungsten bulk layer on the tungsten nucleation layer by alternately supplying a tungsten-containing gas and a reducing gas into the process chamber, and performing a second operation for stopping the supply of the tungsten-containing gas and the reducing gas and removing a remaining gas in the process chamber may be provided. The first operation and the second operation may be repeated at least twice until the tungsten bulk layer reaches a desired thickness.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A method of operating a memory system includes classifying numbers of total error bits into a plurality of ranges, assigning a plurality of data to the plurality of ranges, respectively, counting a number of detected error bits for a memory cell block, and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.

Abstract: A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a memory cell array at the time of a read operation of the memory cells and a controller for controlling the voltage supplier to set and supply a bulk voltage depending on a number of erase/program cycles of the memory cell array.

Abstract: A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.