Abstract: Disclosed is a positive electrode for a lithium-sulfur battery. The positive electrode includes a sulfur-carbon composite as a positive electrode active material. The sulfur-carbon composite includes a porous carbonaceous material having a high porosity and high specific surface area. Therefore, when the sulfur-carbon composite is applied to a battery, the battery shows a reduced initial irreversible capacity and improved output characteristics and life characteristics.

Abstract: Disclosed is a positive electrode for a lithium-sulfur battery, including a sulfur-carbon composite as a positive electrode active material. The sulfur-carbon composite includes a porous carbonaceous material having a high specific surface area, and the total pore volume in the carbonaceous material and a volume of pores having a specific diameter are controlled to specific ranges. Also disclosed is a lithium-sulfur battery using the sulfur-carbon composite. The lithium-sulfur battery shows reduced initial irreversible capacity and improved output characteristics and life characteristics.

Abstract: A positive electrode for a lithium-sulfur battery is provided. The positive electrode includes a positive electrode active material comprising a first and second sulfur-carbon composites respectively comprising a first and a second carbonaceous materials having a different specific surface area and pore volume from each other, and provides reduced initial irreversible capacity and improved output characteristics and life characteristics of a secondary battery.

Abstract: A method for preparing a sulfur-carbon composite including a step of pretreating a carbon material is provided. The method is capable of removing water and other impurities from the carbon material effectively, and the sulfur-carbon composite obtained by the method used as a positive electrode active material of a lithium-sulfur battery provides improved sulfur supportability and over-voltage performance of the lithium-sulfur battery, reduced initial irreversible capacity of the positive electrode active material, and improved output characteristics and life characteristics.

Abstract: A stack type semiconductor device including a first wafer and a second wafer. The first wafer including at least one first chip. The second wafer including at least one second chip electrically connected with the first chip. Each of the first and second chips including a test circuit block, at least one test bonding pad and a hybrid boning member. The test circuit block performing a test operation based on a test signal. The test bonding pad arranged on a bonding surface of each of the first and second chips to transmit the test signal and signals for driving the test circuit block between the first and second chips. The hybrid bonding member electrically connected between the test bonding pads.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad.

Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.

Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.

Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.

Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.