Patents by Inventor Seong Il O

Seong Il O has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180052787
    Abstract: A memory system that supports an offset command includes a memory controller and a memory device. The memory controller may issue an offset command to the memory device for one cycle of a clock signal, the offset command does not include an access address signal, but includes an offset signal from which the access address signal can be derived. The memory device may receive the offset command and may generate an access address signal based on the offset signal of the offset command.
    Type: Application
    Filed: August 21, 2017
    Publication date: February 22, 2018
    Inventors: Jong-pil Son, Seong-il O
  • Patent number: 9767887
    Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: September 19, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Young Hoon Son, Jung Ho Ahn, Seong Il O
  • Publication number: 20160240242
    Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.
    Type: Application
    Filed: June 9, 2015
    Publication date: August 18, 2016
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hoon SON, Jung Ho AHN, Seong Il O