Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.

Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.

Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.

Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.

Abstract: Provided herein are a memory system and method of operating the memory system, which have improved reliability. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks, reading data from the at least one page corresponding to the program address and transmitting the program command and the program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value.

Abstract: Provided herein are a memory system and method of operating the memory system, which have improved reliability. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks, reading data from the at least one page corresponding to the program address and transmitting the program command and the program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value.

Abstract: The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit: suitable for performing an erase operation and a program operation to the memory cell array, and a control logic suitable for controlling the peripheral circuit to erase all of the plurality of memory blocks and then to program the plurality of memory blocks with dummy data during the erase operation.

Abstract: The present disclosure relates to a memory system and an operating method thereof. A memory system may include a semiconductor memory device including a cam block and a normal memory block, and a controller suitable for setting an initial setting read voltage according to an option parameter stored in the cam block and controlling the semiconductor memory device to perform a first read operation to the normal memory block according to the initial setting read voltage.

Abstract: The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit: suitable for performing an erase operation and a program operation to the memory cell array, and a control logic suitable for controlling the peripheral circuit to erase all of the plurality of memory blocks and then to program the plurality of memory blocks with dummy data during the erase operation.

Abstract: A NAND flash memory device includes a semiconductor substrate having a drain select transistor; a source select transistor, and memory cell transistors connected in series between the drain select transistor and the source select transistor, and an oxide film formed in the semiconductor substrate at each of a first side and a second side of a gate of the source select transistor. A method of manufacturing a NAND flash memory device includes providing the semiconductor substrate and forming the oxide film in the semiconductor substrate at each of the first side and the second side of the gate of the source select transistor.

Abstract: A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. A source/drain region is formed below each of the first and second surfaces laterally adjacent to a gate prevailed on the matter surface. A first contact is formed of a conductive material formed on an upper surface of the source/drain region, and a second contact is formed of a conductive material formed on the gate, so that it is possible to prevent a punch through phenomenon, increase the integrity of the device, and decrease the contact resistance of a contact formed on the gate.

Abstract: A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. A source/drain region is formed below each of the first and second surfaces laterally adjacent to a gate prevailed on the matter surface. A first contact is formed of a conductive material formed on an upper surface of the source/drain region, and a second contact is formed of a conductive material formed on the gate, so that it is possible to prevent a punch through phenomenon, increase the integrity of the device, and decrease the contact resistance of a contact formed on the gate.

Abstract: A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. A source/drain region is formed below each of the first and second surfaces laterally adjacent to a gate prevailed on the matter surface. A first contact is formed of a conductive material formed on an upper surface of the source/drain region, and a second contact is formed of a conductive material formed on the gate, so that it is possible to prevent a punch through phenomenon, increase the integrity of the device, and decrease the contact resistance of a contact formed on the gate.