Abstract: Provided are a method for generating steerable realistic image content according to an embodiment and a motion simulation system thereof. A device for generating steerable realistic image content according to an embodiment includes at least one processor and a memory configured to store at least one program which is executed by the at least one processor, wherein the processor is configured to acquire a motion path in a realistic image captured by a camera while the camera is moving along a predetermined path, generate a 3-dimensional (3D) motion model based on the motion path, and synchronize the 3D motion model with the realistic image, and the 3D motion model includes a 3D moving object which moves along a 3D motion path generated along 3D coordinates of the motion path.

Abstract: A present invention relates to a digital doorlock including a latch bolt self-loosening structure which includes an authenticator which receives an authentication signal and performs authentication; a motor which is driven in a predetermined direction when authentication is performed by the authenticator; a latch operator which can be operated through driving of the motor; and a shaft which is rotated according to operation of the latch operator and operates a latch bolt, wherein the latch operator releases the latch bolt by operating according to the authentication and rotating the shaft in one direction.

Abstract: One embodiment of the present disclosure relates to a push-pull structure. According to one embodiment of the present disclosure, there is provided a push-pull structure including a first mobile portion and a second mobile portion installed at a handle portion, a first pivoting portion that pivots due to a movement of the first mobile portion and a second pivoting portion that pivots due to the second mobile portion, a connector that connects the first pivoting portion with the second pivoting portion, a pivoting body linked with the connector and connected to a mortise to fasten or release a latch, a reaction structure disposed in the connector and including an elastic member, and a switching member separated from or mounted on the reaction structure. Here, a position of the elastic member is changed by the switching member.

Abstract: A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.

Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.

Abstract: A display driver integrated circuit (IC) includes a first driver block, a second driver block, and a transmission control circuit. The transmission control circuit is configured to deserialize pixel data groups of a serial data packet and to alternate sending the deserialized pixel data groups to the first driver block and the second driver block. Each of the pixel data groups includes pixel data for at least one pixel.

Abstract: A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.

Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.

Abstract: A data output driver, for use in a semiconductor memory device, includes a pull-up driving unit, having N numbers of unit pull-up drivers and N numbers of pull-up resistors, turned on by selected pull-up control signals for pull-up driving the output terminal in response to a pull-up data signal; and a pull-down driving unit, having N numbers of unit pull-down drivers and N numbers of pull-down resistors, turned on by selected pull-down control signals for pull-down driving the output terminal in response to a pull-down data signal, wherein each of the N numbers of unit pull-up drivers has the same driving strength, and the N numbers of pull-up resistors are connected between the output terminal and the N numbers of unit pull-up drivers; and each of the N numbers of unit pull-down drivers has the same driving strength, and the N numbers of pull-down resistors are connected between the output terminal and the N numbers of unit pull-down drivers.

Abstract: A semiconductor memory device comprises a data input/output pad; a data input unit for buffering and latching a data signal inputted through the data input/output pad during a data access operation, or for buffering and latching an OCD control code signal inputted through the data input/output pad during the OCD calibration control operation; a data align unit for aligning the data signal latched by the data input unit and transferring the aligned data signal to a memory core during the data access operation, or for aligning and outputting the OCD control code signal latched by the data input unit during the OCD calibration control operation; a data output driver for outputting and driving the data signal outputted from the memory core; and an OCD control unit for decoding the OCD control code signal outputted from the data align unit to thereby adjust an output impedance of the data output driver.

Abstract: A data output driver, for use in a semiconductor memory device, includes a pull-up driving unit, having N numbers of unit pull-up drivers and N numbers of pull-up resistors, turned on by selected pull-up control signals for pull-up driving the output terminal in response to a pull-up data signal; and a pull-down driving unit, having N numbers of unit pull-down drivers and N numbers of pull-down resistors, turned on by selected pull-down control signals for pull-down driving the output terminal in response to a pull-down data signal, wherein each of the N numbers of unit pull-up drivers has the same driving strength, and the N numbers of pull-up resistors are connected between the output terminal and the N numbers of unit pull-up drivers; and each of the N numbers of unit pull-down drivers has the same driving strength, and the N numbers of pull-down resistors are connected between the output terminal and the N numbers of unit pull-down drivers.

Abstract: A semiconductor memory device comprises a data input/output pad; a data input unit for buffering and latching a data signal inputted through the data input/output pad during a data access operation, or for buffering and latching an OCD control code signal inputted through the data input/output pad during the OCD calibration control operation; a data align unit for aligning the data signal latched by the data input unit and transferring the aligned data signal to a memory core during the data access operation, or for aligning and outputting the OCD control code signal latched by the data input unit during the OCD calibration control operation; a data output driver for outputting and driving the data signal outputted from the memory core; and an OCD control unit for decoding the OCD control code signal outputted from the data align unit to thereby adjust an output impedance of the data output driver.