Abstract: A multi-chip system and a boot code fetch method include a nonvolatile memory chip storing a volatile memory chip, and a boot code, and a host fetching the boot code. The boot code is transferred to the volatile memory chip before the host fetches the boot code in the nonvolatile memory chip, and the boot code is fetched in the volatile memory chip. Therefore, a bootRAM of the conventional nonvolatile memory chip may be removed, so that an area of the nonvolatile memory chip can be reduced.

Abstract: A flash memory device for performing a bad block management and a method of performing bad block management are implemented in hardware level. During a booting procedure of a flash memory device, a bad block-mapping table stored in a predetermined block of memory cell array unit or other nonvolatile memory is stored in a bad block mapping register via a bad block-mapping table loader. An address selector receives a logical address from an external device and compares the logical address with a bad block address stored in the bad block mapping register. A bad block-state controller determines a count number of a re-mapping mark and outputs a re-mapping mark flag to the address selector. The address selector selects a logical address or a bad block address received from the bad block mapping register as a physical address and outputs the physical address to the memory cell array unit.

Abstract: Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program operation. A second address for selecting a memory block is received and latched, which is repeated until second addresses of memory blocks to be selected are all received and latched. Memory blocks are selected by the latched second addresses, and then the same rows of the respective selected memory blocks are simultaneously activated according to the first address. Related memory devices also are described.

Abstract: Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored. Then, the rows selected by the temporarily stored addresses may be simultaneously activated, and at least some of the memory cells in the activated rows are simultaneously programmed. Corresponding non-volatile memory devices are also provided.

Abstract: The disclosure is a method of controlling operations in a static random access memory employing twin cells. After a wordline coupled to first and second cell transistors is conductive, a voltage difference between a first bitline, which is connected to a first cell capacitor through the first cell transistor, and a second bitline, which is connected to a second cell capacitor through the second cell transistor, is driven into a sense amplifier to be developed with amplification. An active wordline turns nonconductive when one of the bitline voltages accords with a predetermined reference voltage.

Abstract: An SRAM device according to the present invention includes at least one twin cell to which first and second bitlines are coupled. The first and second bitlines are precharged to a power supply voltage for an array via a sense and amplifier circuit before/after a read, write or refresh operation.

Abstract: An apparatus and method for controlling a refresh operation of a memory device capable of performing an internal refresh after a power-up sequence is completed. The apparatus an apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprises a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.

Abstract: An SRAM device according to the present invention includes at least one twin cell to which first and second bitlines are coupled. The first and second bitlines are precharged to a power supply voltage for an array via a sense and amplifier circuit before/after a read, write or refresh operation.

Abstract: The disclosure is a method of controlling operations in a static random access memory employing twin cells. After a wordline coupled to first and second cell transistors is conductive, a voltage difference between a first bitline, which is connected to a first cell capacitor through the first cell transistor, and a second bitline, which is connected to a second cell capacitor through the second cell transistor, is driven into a sense amplifier to be developed with amplification. An active wordline turns nonconductive when one of the bitline voltages accords with a predetermined reference voltage.

Abstract: An apparatus and method for controlling a refresh operation of a memory device capable of performing an internal refresh after a power-up sequence is completed. The apparatus an apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprises a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.

Abstract: An integrated circuit device includes a package and an externally accessible signal lead attached to the package. An integrated circuit chip is mounted in the package and connected to the signal lead. The integrated circuit chip includes a mode-selective signal generating circuit configured to receive a mode control signal and an internal signal and coupled to the externally accessible signal lead. The mode-selective signal generating circuit is operative to produce an output signal responsive to one of the internal signal or an external signal applied to the externally accessible signal lead based on the mode control signal. According to an embodiment, the integrated circuit chip further includes a memory circuit including a sense amplifier that senses a bit line voltage in response to a sense enable signal. The internal signal includes a sense enable control signal having a timing adapted for sensing a bit line voltage in a memory cycle of the memory circuit.

Abstract: A refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation is provided. In the refresh method for a semiconductor memory device, when refresh operation is requested, the low address for the refresh operation is latched, and it is determined whether a normal operation command is inputted into the semiconductor memory device. If the normal operation command is inputted into the device, block selection bits of a low address for normal operation is compared with block selection bits of the latched low address for the refresh operation. When block selection bits of both low addresses are the same, a word line for the refresh operation is activated by decoding the latched low address for the refresh operation. A word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for refresh operation is decoded.

Abstract: A refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation is provided. In the refresh method for a semiconductor memory device, when refresh operation is requested, the low address for the refresh operation is latched, and it is determined whether a normal operation command is inputted into the semiconductor memory device. If the normal operation command is inputted into the device, block selection bits of a low address for normal operation is compared with block selection bits of the latched low address for the refresh operation. When block selection bits of both low addresses are the same, a word line for the refresh operation is activated by decoding the latched low address for the refresh operation. A word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for refresh operation is decoded.

Abstract: Integrated circuit memory devices monitor clock signal transitions and automatically induce a power saving standby mode of operation if the clock signal becomes inactive for a designated amount of time. The memory devices include at least one buffer having an active mode and an inactive standby mode and a standby current control circuit. This control circuit disposes the at least one buffer in its inactive standby mode whenever a power down signal is in a first logic state or whenever the power down signal is in a second logic state at a point in time when a clock signal has continuously been in an inactive state for a duration greater than twice its period. The control circuit may comprise a clock signal detector having N serially-connected latches therein which are reset whenever the clock signal transitions from the inactive state to an active state.