Patents by Inventor Seongmin Son
Seongmin Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240274593Abstract: A semiconductor device includes a first substrate structure and a second substrate structure stacked on the first substrate structure. The first substrate structure includes a plurality of first bonding pads in a first die region of a first substrate, a first passivation layer on the first substrate and exposing the first bonding pads, and a plurality of first dummy patterns in the first passivation layer in a first scribe region. The second substrate structure includes a plurality of second bonding pads in a second die region of a second substrate, a second passivation layer on the second substrate and exposing the second bonding pads, and a plurality of second dummy patterns in the second passivation layer in a second scribe region. The first bonding pad and the second bonding pad are directly bonded to each other.Type: ApplicationFiled: January 17, 2024Publication date: August 15, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Seongmin SON, Seokho KIM, Sumin PARK, Kyuha LEE, Joohee JANG
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Patent number: 11887841Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad.Type: GrantFiled: March 8, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuha Lee, Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son, Yikoan Hong
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Patent number: 11658139Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.Type: GrantFiled: March 19, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaehyung Park, Seokho Kim, Hoonjoo Na, Seongmin Son, Kyuha Lee, Yikoan Hong
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Publication number: 20220068852Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.Type: ApplicationFiled: October 14, 2021Publication date: March 3, 2022Inventors: Ju-Il CHOI, Pil-Kyu KANG, Hoechul KIM, Hoonjoo NA, Jaehyung PARK, Seongmin SON
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Publication number: 20220037273Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.Type: ApplicationFiled: March 19, 2021Publication date: February 3, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jaehyung Park, Seokho Kim, Hoonjoo Na, Seongmin Son, Kyuha Lee, Yikoan Hong
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Publication number: 20220013502Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad.Type: ApplicationFiled: March 8, 2021Publication date: January 13, 2022Inventors: Kyuha Lee, Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son, Yikoan Hong
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Patent number: 11152317Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.Type: GrantFiled: May 7, 2019Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Il Choi, Pil-Kyu Kang, Hoechul Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son
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Publication number: 20200098711Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.Type: ApplicationFiled: May 7, 2019Publication date: March 26, 2020Inventors: Ju-Il CHOI, Pil-Kyu KANG, Hoechul KIM, Hoonjoo NA, Jaehyung PARK, Seongmin SON
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Patent number: 9847276Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.Type: GrantFiled: August 19, 2014Date of Patent: December 19, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil-Kyu Kang, Byung Lyul Park, SungHee Kang, Taeseong Kim, Taeyeong Kim, Kwangjin Moon, Jae-Hwa Park, Sukchul Bang, Seongmin Son, Jin Ho An, Ho-Jin Lee, Jeonggi Jin
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Patent number: 9153559Abstract: A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed.Type: GrantFiled: September 11, 2012Date of Patent: October 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dosun Lee, Byung Lyul Park, Gilheyun Choi, Kwangjin Moon, Kunsang Park, Sukchul Bang, Seongmin Son
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Publication number: 20150137326Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.Type: ApplicationFiled: August 19, 2014Publication date: May 21, 2015Inventors: Pil-Kyu KANG, Byung Lyul PARK, SungHee KANG, TAESEONG KIM, TAEYEONG KIM, KWANGJIN MOON, Jae-Hwa PARK, SUKCHUL BANG, Seongmin SON, JIN HO AN, Ho-Jin LEE, JEONGGI JIN
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Publication number: 20130127019Abstract: A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed.Type: ApplicationFiled: September 11, 2012Publication date: May 23, 2013Inventors: Dosun LEE, Byung Lyul Park, Gilheyun Choi, Kwangjin Moon, Kunsang Park, Sukchul Bang, Seongmin Son
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Patent number: D1041110Type: GrantFiled: August 26, 2022Date of Patent: September 3, 2024Assignee: LG ELECTRONICS INC.Inventors: Nerry Son, Hoil Jeon, Seongmin Kim, Jaeyoung Kim