Patents by Inventor Seongmin Son

Seongmin Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274593
    Abstract: A semiconductor device includes a first substrate structure and a second substrate structure stacked on the first substrate structure. The first substrate structure includes a plurality of first bonding pads in a first die region of a first substrate, a first passivation layer on the first substrate and exposing the first bonding pads, and a plurality of first dummy patterns in the first passivation layer in a first scribe region. The second substrate structure includes a plurality of second bonding pads in a second die region of a second substrate, a second passivation layer on the second substrate and exposing the second bonding pads, and a plurality of second dummy patterns in the second passivation layer in a second scribe region. The first bonding pad and the second bonding pad are directly bonded to each other.
    Type: Application
    Filed: January 17, 2024
    Publication date: August 15, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seongmin SON, Seokho KIM, Sumin PARK, Kyuha LEE, Joohee JANG
  • Patent number: 11887841
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyuha Lee, Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son, Yikoan Hong
  • Patent number: 11658139
    Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Park, Seokho Kim, Hoonjoo Na, Seongmin Son, Kyuha Lee, Yikoan Hong
  • Publication number: 20220068852
    Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Inventors: Ju-Il CHOI, Pil-Kyu KANG, Hoechul KIM, Hoonjoo NA, Jaehyung PARK, Seongmin SON
  • Publication number: 20220037273
    Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.
    Type: Application
    Filed: March 19, 2021
    Publication date: February 3, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyung Park, Seokho Kim, Hoonjoo Na, Seongmin Son, Kyuha Lee, Yikoan Hong
  • Publication number: 20220013502
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad.
    Type: Application
    Filed: March 8, 2021
    Publication date: January 13, 2022
    Inventors: Kyuha Lee, Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son, Yikoan Hong
  • Patent number: 11152317
    Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Il Choi, Pil-Kyu Kang, Hoechul Kim, Hoonjoo Na, Jaehyung Park, Seongmin Son
  • Publication number: 20200098711
    Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.
    Type: Application
    Filed: May 7, 2019
    Publication date: March 26, 2020
    Inventors: Ju-Il CHOI, Pil-Kyu KANG, Hoechul KIM, Hoonjoo NA, Jaehyung PARK, Seongmin SON
  • Patent number: 9847276
    Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-Kyu Kang, Byung Lyul Park, SungHee Kang, Taeseong Kim, Taeyeong Kim, Kwangjin Moon, Jae-Hwa Park, Sukchul Bang, Seongmin Son, Jin Ho An, Ho-Jin Lee, Jeonggi Jin
  • Patent number: 9153559
    Abstract: A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dosun Lee, Byung Lyul Park, Gilheyun Choi, Kwangjin Moon, Kunsang Park, Sukchul Bang, Seongmin Son
  • Publication number: 20150137326
    Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 21, 2015
    Inventors: Pil-Kyu KANG, Byung Lyul PARK, SungHee KANG, TAESEONG KIM, TAEYEONG KIM, KWANGJIN MOON, Jae-Hwa PARK, SUKCHUL BANG, Seongmin SON, JIN HO AN, Ho-Jin LEE, JEONGGI JIN
  • Publication number: 20130127019
    Abstract: A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed.
    Type: Application
    Filed: September 11, 2012
    Publication date: May 23, 2013
    Inventors: Dosun LEE, Byung Lyul Park, Gilheyun Choi, Kwangjin Moon, Kunsang Park, Sukchul Bang, Seongmin Son
  • Patent number: D1041110
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: September 3, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Nerry Son, Hoil Jeon, Seongmin Kim, Jaeyoung Kim