Abstract: Disclosed are a substrate processing apparatus and a substrate processing method capable of improving processing uniformity of a substrate. The substrate processing apparatus includes a body configured to spin-rotate; a plurality of support pins installed on the body so as to support the substrate thereon; a plurality of chuck pins installed on the body so as to grip a side surface of the substrate; a chuck pin driver device configured to move the chuck pin from a stand-by position to a grip position when the substrate has been seated on the support pin; and a support pin spacing device configured to space the substrate and at least one of the support pins from each other while the chuck pin is gripping the substrate.

Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on a refresh rate control signal. Thus, the display device provides improved visibility.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.