Abstract: A method for generating a key stream according to an embodiment includes generating r round keys that are each N-dimensional integer vectors including elements of an integer set defined based on a prime number t, based on a random bit string, an encryption counter, and a secret key that is an N-dimensional integer vector consisting of elements of the integer set , generating a first round output vector x1 by performing a modular addition operation on an initial vector and a first round key RK1 of the r round keys with the prime number t as a modulus, and generating a key stream that is an N-dimensional integer vector consisting of elements of the integer set from the first round output vector x1 by using a second to r-th round keys of the r round keys, and one or more first round functions and a second round function.

Abstract: A method for protecting data based on a private set union (PSU) protocol includes: generating a Boolean vector for a first information set, based on whether or not each of a plurality of first groups that are groups of elements of the first information set stored in a first computing device is the same as each of a plurality of second groups that are groups of elements of a second information set stored in a second computing device, obtaining a random vector for the first information set as a result of shuffling performed by using the Boolean vector generated by the first computing device as an input and using order information and encryption information selected by the second computing device as inputs, and generating information on a union of the first information set and the second information set based on the random vector.

Abstract: An example embodiment provides a calculating method using a zero-knowledge proof-friendly one-way function, performed by a computing device, the calculating method including: calculating a first intermediate bit stream by inputting an input bit stream of a one-way function to an augmented matrix, calculating a second intermediate bit stream by dividing the first intermediate bit stream into a predetermined number of bit streams and inputting each of the predetermined number of divided bit streams to a substitution-box (S-box), and outputting an output bit stream of the one-way function by inputting the second intermediate bit stream to a reduced matrix.

Abstract: Various embodiments relate to a stackable 3D artificial neural network device and a manufacturing method thereof. According to various embodiments, a device is manufactured to include a substrate, a neuron block placed on some areas on one side of the substrate, a synapse block placed on the rest of the areas on one side of the substrate, and the neuron block and the synapse block may include at least one first channel element arranged on one side of the substrate and at least one second channel element stacked on the first channel element.

Abstract: A method for encryption according to an embodiment includes generating a ciphertext for a secret key that is an integer vector by using an integer-based first homomorphic encryption algorithm, generating a key stream that is the integer vector from a nonce and the secret key by using a key stream generator, encoding the key stream by using a message encoding function of the first homomorphic encryption algorithm, encoding a message that is a real vector by using a message encoding function of a real number-based second homomorphic encryption algorithm, generating a ciphertext for the message by using a result of the encoding of the key stream and a result of the encoding of the message, and transmitting the nonce, the ciphertext for the secret key, and the ciphertext for the message to an apparatus for converting a ciphertext.

Abstract: A method for generating a key stream according to an embodiment includes generating r round keys that are each N-dimensional integer vectors including elements of an integer set defined based on a prime number t, based on a random bit string, an encryption counter, and a secret key that is an N-dimensional integer vector consisting of elements of the integer set , generating a first round output vector x1 by performing a modular addition operation on an initial vector and a first round key RK1 of the r round keys with the prime number t as a modulus, and generating a key stream that is an N-dimensional integer vector consisting of elements of the integer set from the first round output vector x1 by using a second to r-th round keys of the r round keys, and one or more first round functions and a second round function.

Abstract: A method for encryption according to an embodiment includes generating a ciphertext for a secret key that is an integer vector by using an integer-based first homomorphic encryption algorithm, generating a key stream that is the integer vector from a nonce and the secret key by using a key stream generator, encoding the key stream by using a message encoding function of the first homomorphic encryption algorithm, encoding a message that is a real vector by using a message encoding function of a real number-based second homomorphic encryption algorithm, generating a ciphertext for the message by using a result of the encoding of the key stream and a result of the encoding of the message, and transmitting the nonce, the ciphertext for the secret key, and the ciphertext for the message to an apparatus for converting a ciphertext.

Abstract: Various embodiments relate to a stackable 3D artificial neural network device and a manufacturing method thereof. According to various embodiments, a device is manufactured to include a substrate, a neuron block placed on some areas on one side of the substrate, a synapse block placed on the rest of the areas on one side of the substrate, and the neuron block and the synapse block may include at least one first channel element arranged on one side of the substrate and at least one second channel element stacked on the first channel element.

Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.

Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.

Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.

Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.