Abstract: According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.

Abstract: According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.

Abstract: A semiconductor device may include a substrate, which includes a logic cell region including first and second active regions and a test region including dummy regions, first and second active patterns provided on the first and second active regions, respectively, a dummy pattern provided on each of the dummy regions, a device isolation layer disposed in trenches defining each of the dummy pattern and the first and second active patterns, a contact pattern provided on the dummy pattern, a gate electrode provided to cross the dummy regions, a gate contact coupled to the gate electrode, and a metal layer on the gate contact. The metal layer may include two test lines provided on the test region and respectively coupled to the contact pattern and the gate contact. A top surface of the first active pattern may be lower than a top surface of the dummy pattern.