Abstract: A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Abstract: One embodiment of the present invention provides a system that facilitates routing integrated circuit traces to reduce inductive noise coupling. Upon receiving an integrated circuit layout, the system routes traces between circuit elements of the integrated circuit through multiple layers of the integrated circuit layout. In doing so, the system groups traces together within each layer and separates each group from adjacent groups in the same layer using a shield trace. The system also routes a nearby shield trace on a nearby layer so that the nearby shield trace runs parallel to and is substantially centered on a group of traces within the layer. In this way, the nearby shield trace also provides inductive shielding for the group of traces.

Abstract: One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

Abstract: One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

Abstract: One embodiment of the present invention provides a system that facilitates detecting one or more slow nodes in an integrated circuit layout. During operation, the system receives an integrated circuit layout. Next, the system inserts repeaters into signal lines of the integrated circuit layout to define a set of nets. The system then produces a resistance/capacitance (R/C) model for each net and obtains a timing model for each driver and receiver in the integrated circuit layout. This timing model specifies a non-linear circuit model for each driver and a non-linear circuit model for each receiver in the layout. The system then performs a circuit simulation using the timing model for each driver and receiver and the R/C model for each net. The system uses results of this circuit simulation to identify one or more slow nodes in the integrated circuit layout.

Abstract: An apparatus coupled to a requesting unit and a memory. The apparatus includes a data path and a request control circuit. The data path is coupled to the requesting unit and the memory. The data path is for buffering a vector. The vector includes multiple data elements of a substantially similar data type. The request control circuit is coupled to the data path and the requesting unit. The request control circuit is for receiving a vector memory request from the requesting unit. The request control circuit services the vector memory request by causing the transference of the vector between the requesting unit and the memory via the data path.