Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.

Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.