Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: An alloy material is formed on an underlying material, and the alloy material comprises an alloy doping element mixed into a bulk material. A first layer of material including the alloy doping element is deposited on the underlying material using a first type of deposition process. The first type of deposition process is corrosion resistive to the underlying material according to one aspect of the present invention. A second layer of material including the bulk material is deposited on the first layer of material using a second type of deposition process. A thermal anneal may be performed by heating the first layer of material and the second layer of material such that the alloy doping element is mixed into the bulk material to form the alloy material on the underlying material. The alloy doping element of the first layer of material deposited on the underlying material promotes adhesion of the alloy material to the underlying material.

Abstract: A method of fabricating a semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects by cost-effectively removing the contaminant layer and a device thereby formed.

Abstract: In one embodiment, a method for manufacturing a field effect transistor (100) includes forming a polysilicon gate (104) on a surface (106) of a semiconductor substrate (102) in association with adjacent source/drain regions (110, 112) and forming dielectric spacers (124, 126) on sides of the polysilicon gate. The method further includes forming a trench (202) between the dielectric spacers on a surface (200) of the polysilicon gate and filling at least a portion of the trench with barrier and copper or other high conductivity metal to form a copper-polysilicon gate of the field effect transistor.

Abstract: The present invention relates to a method for forming in-laid copper metallization capacitors in a trench serpentine form. In one aspect of the present invention, the method includes providing a semiconductor substrate having at least one trench formed therein. A first metal layer is deposited conformally onto a trench and substrate surface. The first metal layer is then anodized to form a conformal bilayer comprising an anodic (metal) oxide layer formed over the first metal layer. A copper-conductive metal layer is then deposited conformally over the metal oxide layer to facilitate electroplating of the trench and substrate surface. The trench and substrate surface is then electroplated with copper whereby the at least one trench is filled with copper.

Abstract: A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening.

Abstract: A method of fabricating a semiconductor device having a Cu—Ca—O thin film formed on a Cu surface by immersing the Cu surface into a unique chemical (electroless plating) solution containing salts of calcium (Ca) and copper (Cu), their complexing agents, a reducing agent, a pH adjuster, and surfactants; and a semiconductor device thereby formed for improving Cu interconnect reliability, electromigration resistance, and corrosion resistance. The method controls the parameters of pH, temperature, and time in order to form a uniform conformal Cu-rich Cu—Ca—O thin film, possibly containing carbon (C) and/or sulphur (S), for reducing -electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.

Abstract: A method of forming a superconducting damascene interconnect structure, and the structure made thereby, the method includes forming a cavity in an interlevel dielectric; forming a barrier layer in the cavity; forming a seed layer in the cavity over the barrier layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the barrier layer. In one embodiment, the superconductor has a formula YBa2Cu3O7-x, wherein x≦0.5. In another embodiment, the method includes forming a cavity in an interlevel dielectric; forming a Y—Ba—Cu alloy layer in the cavity; forming a seed layer in the cavity over the Y—Ba—Cu alloy layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy fill; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the dielectric.

Abstract: A semiconductor structure includes a conductive metal layer having provided thereover in succession a silicon nitride layer, a dielectric layer, and another silicon nitride layer. An aluminum layer is deposited over the silicon nitride layer. The aluminum layer is selectively anodized so that a top portion of porous aluminum oxide is formed over the remaining aluminum. A reactive ion etch is undertaken through the pores of the aluminum oxide to render the remaining aluminum and silicon nitride layer therebelow porous. The aluminum oxide and aluminum are removed, and the remaining porous silicon nitride layer is used as a template or mask for further reactive ion etching therethrough to the dielectric layer, so that the dielectric layer is rendered porous, thereby lowering its dielectric constant. As an alternative, reactive ion etching of the dielectric can be undertaken with the porous aluminum oxide layer and porous aluminum layer in place.

Abstract: A method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semi conductor device thereby formed. The method reduces the drift velocity which then decreases the Cu migration rate in addition to void formation rate.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: A selected passivating layer is purposely formed on an exposed surface of a Cu and/or Cu alloy interconnect member, thereby avoiding the adverse consequences stemming from formation of a thick copper oxide layer thereon. The passivating layer is formed by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) with a copper corrosion-inhibiting chemical; or (b) by electroless plating a metal layer on the surface of the Cu or Cu alloy layer; or (c) depositing a metallic compound on the surface of the Cu or Cu alloy layer by CVD. The passivating layer can then be removed. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in an ILD, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the passivating, layer thereon, and depositing a silicon nitride diffusion barrier layer thereon.

Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide.

Abstract: A dielectric layer has an opening which communicates with a metal line therebeneath. A layer of silver is deposited over the structure and into the opening, and copper is deposited by electroplating in the opening. An additional silver layer is the deposited, and an anneal step is undertaken so that the copper is surrounded or encapsulated by alloy containing copper and silver. After removal of appropriate portions of the silver layers, the copper remains encapsulated or encased by copper-silver alloy.

Abstract: A method of fabricating a semiconductor device having a Cu—Ca—O thin film formed on a Cu surface by immersing the Cu surface into a unique chemical (electroless plating) solution containing salts of calcium (Ca) and copper (Cu), their complexing agents, a reducing agent, a pH adjuster, and surfactants; and a semiconductor device thereby formed for improving Cu interconnect reliability, electromigration resistance, and corrosion resistance. The method controls the parameters of pH, temperature, and time in order to form a uniform conformal Cu-rich Cu—Ca—O thin film, possibly containing carbon (C) and/or sulphur (S), for reducing electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.

Abstract: A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.

Abstract: A method for effectively filling a dual damascene opening having a via hole and a trench that are contiguous openings uses a two step deposition process. The method includes a step of filling the via hole by electroless deposition of a first conductive material into the via hole. A second conductive material is at a bottom wall of the via hole, and the second conductive material at the bottom wall of the via hole acts as an autocatalytic surface during the electroless deposition of the first conductive material within the via hole. The method also includes the step of depositing a seed layer of a third conductive material to cover walls of the trench and includes the step of filling the trench by electroplating deposition of the third conductive material from the seed layer into the trench. The present invention may be used to particular advantage for small geometry integrated circuits when the conductive material filling the via hole and the trench is copper.

Abstract: The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C.

Abstract: An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the conductive fill into the insulating layer that is surrounding the interconnect opening. An alloy material is deposited non-conformally such that the alloy material is deposited substantially only toward a top of the sidewalls of an interconnect opening and substantially only toward a center of the bottom wall of the interconnect opening. The interconnect opening is filled with the conductive material by growing the conductive material from a seed layer of the conductive material to form a conductive fill of the conductive material within the interconnect opening. The semiconductor wafer is heated to anneal the conductive fill within the interconnect opening such that the conductive fill forms into a substantially single grain structure.