Patents by Inventor Sergey N. Zheltov
Sergey N. Zheltov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121480Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: GrantFiled: July 28, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Dmitry N. Budnikov, Igor Igor Chikalov, Sergey N. Zheltov
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Publication number: 20170025131Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: ApplicationFiled: July 28, 2016Publication date: January 26, 2017Inventors: Dmitry N. Budnikov, Igor Igor Chikalov, Sergey N. Zheltov
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Patent number: 9424854Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: GrantFiled: October 7, 2013Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Dmitry N. Budnikov, Igor Igor Chikalov, Sergey N. Zheltov
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Publication number: 20140108021Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: ApplicationFiled: October 7, 2013Publication date: April 17, 2014Inventors: Dmitry N. Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Patent number: 8589154Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: GrantFiled: June 11, 2012Date of Patent: November 19, 2013Assignee: Intel CorporationInventors: Dmitry N. Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Publication number: 20120259645Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: ApplicationFiled: June 11, 2012Publication date: October 11, 2012Inventors: Dmitry N. Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Patent number: 8229741Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: GrantFiled: November 25, 2010Date of Patent: July 24, 2012Assignee: Intel CorporationInventors: Dmitry N Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Patent number: 8032706Abstract: Machine-readable media, methods, apparatus and system for detecting a data access violation are described. In some embodiments, current memory access information related to a current memory access to a memory address by a current user thread may be obtained. It may be determined whether a cache includes a cache entry associated with the memory address. If the cache includes the cache entry associated with the memory address, then, an access history stored in the cache entry and the current memory access information may be analyzed to detect if there is at least one of an actual violation and a potential violation of accessing the memory address.Type: GrantFiled: August 5, 2008Date of Patent: October 4, 2011Assignee: Intel CorporationInventors: Sergey N. Zheltov, Paul Petersen, Zhiqiang Ma
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Patent number: 7983909Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: GrantFiled: September 15, 2003Date of Patent: July 19, 2011Assignee: Intel CorporationInventors: Dmitry N. Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Publication number: 20110071839Abstract: A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.Type: ApplicationFiled: November 25, 2010Publication date: March 24, 2011Inventors: Dmitry N. Budnikov, Igor V. Chikalov, Sergey N. Zheltov
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Patent number: 7685588Abstract: Embodiments of the present invention provide for platform independence, low intrusiveness, and optimal memory usage of the binary instrumentation process by means of employing one procedure (interceptor function) implemented in a high-level programming language to intercept an arbitrary number of functions or blocks of code. Each time a function or code block needs to be intercepted a new copy of the procedure from a provided memory region may be associated with the address of the function or block of code by means of a memory region descriptor and an intercepted function address table. Once activated, the interceptor function may retrieve its current address and, by searching memory region descriptors, determine the region the current address belongs to; the region's base address may then be obtained. A reference to the intercepted function address table may be fetched from the region descriptor; and an index to the intercepted function address table may be computed.Type: GrantFiled: March 28, 2005Date of Patent: March 23, 2010Assignee: Intel CorporationInventors: Sergey N. Zheltov, Stanislav V. Bratanov, Dmitry Eremin
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Publication number: 20100037025Abstract: Machine-readable media, methods, apparatus and system for detecting a data access violation are described. In some embodiments, current memory access information related to a current memory access to a memory address by a current user thread may be obtained. It may be determined whether a cache includes a cache entry associated with the memory address. If the cache includes the cache entry associated with the memory address, then, an access history stored in the cache entry and the current memory access information may be analyzed to detect if there is at least one of an actual violation and a potential violation of accessing the memory address.Type: ApplicationFiled: August 5, 2008Publication date: February 11, 2010Inventors: Sergey N. Zheltov, Paul Petersen, Zhiqiang Ma
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Patent number: 7584404Abstract: A method and apparatus to provide communications over a packet channel, including applying a forward error correction (FEC) code to a first group of data packets to create a coded group of packets by supplementing a set of parity packets to the first group of data packets; and transmitting the first group of data packets, and transmitting the set of corresponding parity packets after the first group of data packets have been transmitted. In response to receiving a positive acknowledgement corresponding to the first group of packets, ceasing to send parity packets corresponding to the first group of packets and sending a second group of data packets dependent on the first group of data packets. In response to not receiving the acknowledgment, not sending the second group of data packets and continuing to transmit the parity packets corresponding to the first group of data packets.Type: GrantFiled: December 19, 2002Date of Patent: September 1, 2009Assignee: Intel CorporationInventors: Igor V. Kozintsev, Michail A. Ilyin, Roman A. Belenov, Sergey N. Zheltov
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Publication number: 20080155510Abstract: Embodiments of the present invention provide for platform independence, low intrusiveness, and optimal memory usage of the binary instrumentation process by means of employing one procedure (interceptor function) implemented in a high-level programming language to intercept an arbitrary number of functions or blocks of code. Each time a function or code block needs to be intercepted a new copy of the procedure from a provided memory region may be associated with the address of the function or block of code by means of a memory region descriptor and an intercepted function address table. Once activated, the interceptor function may retrieve its current address and, by searching memory region descriptors, determine the region the current address belongs to; the region's base address may then be obtained. A reference to the intercepted function address table may be fetched from the region descriptor; and an index to the intercepted function address table may be computed.Type: ApplicationFiled: March 28, 2005Publication date: June 26, 2008Inventors: Sergey N. Zheltov, Stanislav V. Bratanov, Dmitry Eremin
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Patent number: 7007055Abstract: A fast and precise method to perform inverse and forward Discrete Cosine Transform (DCT) is disclosed. The method may be used for implementing a two-dimensional (2D) inverse or forward DCT that operates on an N×M coefficient block and has a higher accuracy than is specified by the IEEE 1180-1990 standard (for the inverse operation). The disclosed method includes the following stages: based on integer operations, a fixed point one dimensional (1D) DCT may be performed on each row of an input coefficient block, an integer-to-single-precision floating point result conversion may be performed, and a single precision floating point 1D DCT may be performed on each column of the coefficient block resulting from the previous stages.Type: GrantFiled: March 12, 2002Date of Patent: February 28, 2006Assignee: Intel CorporationInventors: Sergey N. Zheltov, Stanislav V. Bratanov, Roman A. Belenov, Alexander N. Knyazev
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Patent number: 6891976Abstract: Decoding variable length codes having regular bit pattern prefixes enables faster decoding of variable length codes, especially in systems that provide bit or bit mask search capabilities. An embodiment of the present invention determines a code prefix type, and calculates a length of the code prefix. A first data structure may be provided to associate the maximal number of bits in a variable length code with the length of the code prefix, and to locate further decoding data in accordance with the prefix length and type. A bit stream may be read according to the maximal length obtained. An additional data structure may be provided to retrieve a decoded value and the actual length of a variable length code being decoded. This data structure may be indexed with the value of the bit combination read from the bit stream. In case the actual length of the variable length code is less than the maximal length, the excess bits may be returned to the bit stream.Type: GrantFiled: March 12, 2002Date of Patent: May 10, 2005Assignee: Intel CorporationInventors: Sergey N. Zheltov, Stanislav V. Bratanov
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Publication number: 20040123211Abstract: A method and apparatus to provide communications over a packet channel, including applying a forward error correction (FEC) code to a first group of data packets to create a coded group of packets by supplementing a set of parity packets to the first group of data packets; and transmitting the first group of data packets, and transmitting the set of corresponding parity packets after the first group of data packets have been transmitted. In response to receiving a positive acknowledgement corresponding to the first group of packets, ceasing to send parity packets corresponding to the first group of packets and sending a second group of data packets dependent on the first group of data packets. In response to not receiving the acknowledgment, not sending the second group of data packets and continuing to transmit the parity packets corresponding to the first group of data packets.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Igor V. Kozintsev, Michail A. Ilyin, Roman A. Belenov, Sergey N. Zheltov
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Publication number: 20030177158Abstract: A fast and precise method to perform inverse and forward Discrete Cosine Transform (DCT) is disclosed. The method may be used for implementing a two-dimensional (2D) inverse or forward DCT that operates on an N×M coefficient block and has a higher accuracy than is specified by the IEEE 1180-1990 standard (for the inverse operation). The disclosed method comprises the following stages: based on integer operations, a fixed point one dimensional (1D) DCT may be performed on each row of an input coefficient block, an integer-to-single-precision floating point result conversion may be performed, and a single precision floating point 1D DCT may be performed on each column of the coefficient block resulting from the previous stages.Type: ApplicationFiled: March 12, 2002Publication date: September 18, 2003Inventors: Sergey N. Zheltov, Stanislav V. Bratanov, Roman A. Belenov, Alexander N. Knyazev
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Publication number: 20030174898Abstract: Decoding variable length codes having regular bit pattern prefixes enables faster decoding of variable length codes, especially in systems that provide bit or bit mask search capabilities. An embodiment of the present invention determines a code prefix type, and calculates a length of the code prefix. A first data structure may be provided to associate the maximal number of bits in a variable length code with the length of the code prefix, and to locate further decoding data in accordance with the prefix length and type. A bit stream may be read according to the maximal length obtained. An additional data structure may be provided to retrieve a decoded value and the actual length of a variable length code being decoded. This data structure may be indexed with the value of the bit combination read from the bit stream. In case the actual length of the variable length code is less than the maximal length, the excess bits may be returned to the bit stream.Type: ApplicationFiled: March 12, 2002Publication date: September 18, 2003Inventors: Sergey N. Zheltov, Stanislav V. Bratanov