Patents by Inventor Sergey Ostrikov
Sergey Ostrikov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11722467Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: GrantFiled: February 3, 2022Date of Patent: August 8, 2023Assignee: INFINEON TECHNOLOGIES LLCInventors: Sergey Ostrikov, Stephan Rosner, Clifford Zitlaw
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Patent number: 11567844Abstract: A storage device can include at least one nonvolatile (NV) memory array that includes a first section having a first physical address range, and a second section having a second physical address range. A nonvolatile fault indication can be set to at least a fault state or a no-fault state. A memory watchdog circuit configured to set the fault indication to the fault state in response to an expiration of a predetermined watchdog period, the watchdog period being reset in response to a defer indication. An address mapping circuit can be configured to, in response to the fault indication having the no fault state, mapping input addresses to the first physical addresses range, and in response to the fault indication having the fault state, mapping the same input addresses to the second physical address range. Corresponding methods and systems are also disclosed.Type: GrantFiled: June 23, 2021Date of Patent: January 31, 2023Assignee: INFINEON TECHNOLOGIES LLCInventors: Sergey Ostrikov, Florian Schreiner
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Patent number: 11537389Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.Type: GrantFiled: October 12, 2020Date of Patent: December 27, 2022Assignee: Infineon Technologies LLCInventors: Stephan Rosner, Sergey Ostrikov, Clifford Zitlaw, Yuichi Ise
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Publication number: 20220229748Abstract: A storage device can include at least one nonvolatile (NV) memory array that includes a first section having a first physical address range, and a second section having a second physical address range. A nonvolatile fault indication can be set to at least a fault state or a no-fault state. A memory watchdog circuit configured to set the fault indication to the fault state in response to an expiration of a predetermined watchdog period, the watchdog period being reset in response to a defer indication. An address mapping circuit can be configured to, in response to the fault indication having the no fault state, mapping input addresses to the first physical addresses range, and in response to the fault indication having the fault state, mapping the same input addresses to the second physical address range. Corresponding methods and systems are also disclosed.Type: ApplicationFiled: June 23, 2021Publication date: July 21, 2022Applicant: Infineon Technologies LLCInventors: Sergey Ostrikov, Florian Schreiner
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Publication number: 20220231995Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: ApplicationFiled: February 3, 2022Publication date: July 21, 2022Applicant: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Clifford Zitlaw
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Patent number: 11258772Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: GrantFiled: June 4, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Cliff Zitlaw
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Patent number: 11249689Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.Type: GrantFiled: October 9, 2020Date of Patent: February 15, 2022Assignee: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Avi Avanindra, Hans Van Antwerpen
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Publication number: 20210223995Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.Type: ApplicationFiled: October 9, 2020Publication date: July 22, 2021Applicant: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Avi Avanindra, Hans Van Antwerpen
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Patent number: 11061663Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.Type: GrantFiled: January 6, 2020Date of Patent: July 13, 2021Assignee: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Publication number: 20210026620Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Applicant: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Clifford Zitlaw, Yuichi Ise
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Patent number: 10809944Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.Type: GrantFiled: March 25, 2020Date of Patent: October 20, 2020Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sergey Ostrikov, Stephan Rosner, Avi Avanindra, Hans Van Antwerpen
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Publication number: 20200301698Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.Type: ApplicationFiled: January 6, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Patent number: 10552145Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.Type: GrantFiled: June 11, 2018Date of Patent: February 4, 2020Assignee: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Publication number: 20190386966Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: ApplicationFiled: June 4, 2019Publication date: December 19, 2019Applicant: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Cliff Zitlaw
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Publication number: 20190179625Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.Type: ApplicationFiled: June 11, 2018Publication date: June 13, 2019Applicant: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise