Abstract: A system that has low power recovery capabilities, the system includes: a switch that is adapted to provide a gated power supply to a power gated circuit in response to a control current; and a control signal generator adapted to control an intensity of the control current in response to a reception of a low power period end indicator, a value of the continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of a high switching point buffer that is inputted by the gated supply voltage.

Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.

Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.

Abstract: A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic.

Abstract: A device and method for adjusting an impedance of an output driver of an integrated circuit; the method includes: (i) receiving, by the output driver, a first square wave signal that should be driven by the output driver to provide a second signal; (ii) monitoring, by a monitoring circuit included in the integrated circuit, the second signal during an output driver transient period resulting from a first square wave signal transient to provide a monitoring result; (iii) determining whether to adjust the impedance of the output driver in response to the monitoring result; and (iv) adjusting the impedance of the output driver in response to the determination.

Abstract: A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage.

Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.

Abstract: A device for testing noise immunity of a circuit includes: an analog circuit, an internal stable reference signal source, an internal power supply module to receive a high level voltage supply, and a signal modulator to provide a noisy signal to the power supply module. The power supply module outputs a noisy power supply to the circuit, in response to the noisy signal, and the device outputs a signal representative of a noise immunity of the circuit. A method includes: providing a high level supply voltage to an internal power supply module, receiving signals representative of the performance of an analog circuit, providing a noisy signal to an input of the power supply module, providing a noisy supply voltage to the circuit, by the power supply module, in response to the noisy signal, and evaluating a noise immunity characteristic of the circuit in response to the received signals.

Abstract: A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Abstract: A method and a device, the device has ground voltage elevation compensation capabilities and includes: multiple current consuming components; a positive voltage supply input; a negative voltage supply input; and a compensation circuit, coupled to the negative voltage supply input and to a grounding element; wherein the compensation circuit is adapted to detect a ground voltage elevation resulting from a flow of excess consumption current through the grounding element, and in response couple the negative voltage supply input to the grounding element; wherein the excess current flows through the grounding element due to an increment in a current consumption of a current consuming element of the device.

Abstract: A system that has low power recovery capabilities, the system includes: a switch that is adapted to provide a gated power supply to a power gated circuit in response to a control current; and a control signal generator adapted to control an intensity of the control current in response to a reception of a low power period end indicator, a value of the continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of a high switching point buffer that is inputted by the gated supply voltage.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

Abstract: A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit.

Abstract: A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages.

Abstract: A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage.

Abstract: An arrangement (100) and method for a high precision and low distortion digital delay line with infinite delay. The digital delay line has an oscillating ring (110) with an odd number of inverting elements that triggers a counter (120). A comparator (130) compares the counter and the MSB of a given delay word. A line of inverters (150–159), double the odd number in the ring oscillator, is connected to a MUX (160) controlled by the LSB of the delay word. This provides the advantages of: high resolution due to use of a small, basic component, self-delay ring oscillator; small silicon area due to use of a special decoding scheme use the rings number to produce large delays; and easy implementation as a digital block in an integrated circuit using a standard cells library to build the ring and the decoder.

Abstract: A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analog test circuitry (20) for testing at least one analog element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.