Patents by Inventor Sergey V. Rylov

Sergey V. Rylov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698968
    Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anthony R. Bonaccio, Timothy C. Buchholtz, Rajesh Cheeranthodi, Giri N. Rangan, Sergey V. Rylov
  • Publication number: 20160182216
    Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Anthony R. Bonaccio, Timothy C. Buchholtz, Rajesh Cheeranthodi, Giri N. Rangan, Sergey V. Rylov
  • Patent number: 9306729
    Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anthony R. Bonaccio, Timothy C. Buchholtz, Rajesh Cheeranthodi, Giri N. Rangan, Sergey V. Rylov
  • Patent number: 9253004
    Abstract: An apparatus and method to control signal phase in a radio device includes an analog phase rotator that accepts differential in-phase (I) and quadrature (Q) inputs, connected in two differential pairs. The analog phase rotator is driven by a local oscillator and is configured to control a phase of the local oscillator's output. A phase error determination module is configured to determine phase error information based on received I and Q (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: February 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Troy J. Beukema, Brian A. Floyd, Scott K. Reynolds, Sergey V. Rylov
  • Patent number: 9137070
    Abstract: An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Troy James Beukema, Brian Allan Floyd, Scott Kevin Reynolds, Sergey V. Rylov
  • Publication number: 20150215144
    Abstract: An apparatus and method to control signal phase in a radio device includes an analog phase rotator that accepts differential in-phase (I) and quadrature (Q) inputs, connected in two differential pairs. The analog phase rotator is driven by a local oscillator and is configured to control a phase of the local oscillator's output. A phase error determination module is configured to determine phase error information based on received I and Q (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: TROY J. BEUKEMA, BRIAN A. FLOYD, SCOTT K. REYNOLDS, SERGEY V. RYLOV
  • Publication number: 20150200765
    Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 16, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony R. Bonaccio, Timothy C. Buchholtz, Rajesh Cheeranthodi, Giri N. Rangan, Sergey V. Rylov
  • Patent number: 8928384
    Abstract: A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Sergey V. Rylov
  • Patent number: 8774228
    Abstract: Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Timothy O. Dickson, Daniel J. Friedman, Yong Liu, Sergey V. Rylov
  • Publication number: 20140176213
    Abstract: A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
    Type: Application
    Filed: September 4, 2013
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventor: Sergey V. Rylov
  • Patent number: 8704583
    Abstract: Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Steven M. Clements, Sergey V. Rylov
  • Patent number: 8564352
    Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ankur Agrawal, John F. Bulzacchelli, Sergey V. Rylov
  • Patent number: 8558597
    Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ankur Agrawal, John F. Bulzacchelli, Sergey V. Rylov
  • Patent number: 8552783
    Abstract: A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventor: Sergey V. Rylov
  • Publication number: 20130214865
    Abstract: Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Steven M. Clements, Sergey V. Rylov
  • Publication number: 20130207707
    Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ankur Agrawal, John F. Bulzacchelli, Sergey V. Rylov
  • Publication number: 20130207708
    Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ankur Agrawal, John F. Bulzacchelli, Sergey V. Rylov
  • Publication number: 20120314721
    Abstract: Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JOHN F. BULZACCHELLI, Timothy O. Dickson, Daniel J. Friedman, Yong Liu, Sergey V. Rylov
  • Publication number: 20120313683
    Abstract: A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: SERGEY V. RYLOV
  • Patent number: 8139700
    Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Troy J. Beukema, Steven M. Clements, Chun-Ming Hsu, William R. Kelly, Elizabeth M. May, Sergey V. Rylov