Patents by Inventor Sergey Yuferev
Sergey Yuferev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978692Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.Type: GrantFiled: September 10, 2021Date of Patent: May 7, 2024Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Josef Hoeglauer, Gerhard Noebauer, Hao Zhuang
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Patent number: 11973071Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.Type: GrantFiled: May 4, 2021Date of Patent: April 30, 2024Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Sergey Yuferev
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Patent number: 11935874Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.Type: GrantFiled: July 23, 2021Date of Patent: March 19, 2024Assignee: Infineon Technologies AGInventors: Robert Fehler, Sergey Yuferev
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Publication number: 20240030111Abstract: A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.Type: ApplicationFiled: July 12, 2023Publication date: January 25, 2024Inventors: Sergey Yuferev, Josef Höglauer, Gerhard Thomas Nöbauer, Hao Zhuang
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Publication number: 20230420393Abstract: A semiconductor package includes: a semiconductor die having opposing first and second surfaces, a first contact pad on the first surface, and a second contact pad on the second surface; a die pad and at least one lead spaced apart from the die pad, the first contact pad of the die being mounted on the die pad and the second contact pad being electrically connected to the at least one lead by a connector; a mold compound covering the die, connector, and an upper surface of the die pad and of the at least one lead; and a metallic member inductively coupled to the connector and electrically resistively insulated from the connector. The metallic member includes a web portion arranged above the second surface of the die and at least one peripheral rim portion that extends from the web portion in a direction towards the first surface of the die.Type: ApplicationFiled: June 1, 2023Publication date: December 28, 2023Inventor: Sergey Yuferev
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Publication number: 20230253304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Patent number: 11664304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20220367350Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Patent number: 11444017Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.Type: GrantFiled: September 4, 2019Date of Patent: September 13, 2022Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Patent number: 11348861Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: GrantFiled: September 17, 2020Date of Patent: May 31, 2022Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20220122906Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.Type: ApplicationFiled: September 27, 2021Publication date: April 21, 2022Applicant: Infineon Technologies AGInventors: Sergey YUFEREV, Paul Armand Asentista CALO, Theng Chao LONG, Josef MAERZ, Chee Yang NG, Petteri PALM, Wae Chet YONG
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Publication number: 20220108945Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: ApplicationFiled: October 5, 2021Publication date: April 7, 2022Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20220084915Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.Type: ApplicationFiled: September 10, 2021Publication date: March 17, 2022Inventors: Sergey Yuferev, Josef Hoeglauer, Gerhard Noebauer, Hao Zhuang
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Publication number: 20220028840Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.Type: ApplicationFiled: July 23, 2021Publication date: January 27, 2022Inventors: Robert Fehler, Sergey Yuferev
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Publication number: 20210351168Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.Type: ApplicationFiled: May 4, 2021Publication date: November 11, 2021Inventors: Gerhard Noebauer, Sergey Yuferev
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Publication number: 20210005536Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Patent number: 10811342Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: GrantFiled: February 27, 2019Date of Patent: October 20, 2020Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20200075484Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.Type: ApplicationFiled: September 4, 2019Publication date: March 5, 2020Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20190267309Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: ApplicationFiled: February 27, 2019Publication date: August 29, 2019Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm