Abstract: A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction.

Abstract: A system for, and method of, reference-modeling a processor design. In one embodiment, the system includes: (1) an architecture database that contains specifications regarding the processor design that include: instruction set specifications, architectural resource specifications, pipeline specifications and connectivity specifications, (2) a simulation subsystem that draws selected portions of the specifications to simulate and test the processor design and (3) a documentation subsystem that draws other selected portions of the specifications to document and register-model the processor design, changes in the specifications being propagated to the architecture database.

Abstract: A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes a conditional execution instruction and one or more target instructions. The conditional execution instruction specifies the target instructions, a register, and a register condition, and includes pointer update information. The execution unit saves a result of each of the target instructions dependent upon the existence of the specified register condition during execution of the conditional execution instruction. When a target instruction is an instruction involving a pointer subject to update, the execution unit updates the pointer dependent upon the pointer update information. A system (e.g., a computer system) is described including the processor coupled to a memory system. A method is disclosed for conditionally executing at least one instruction, including inputting the conditional execution instruction and the target instructions.

Abstract: A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condition within the register. The system saves a result of each of the target instructions dependent upon the existence of the condition in the specified register during execution of the conditional execution instruction. When the conditional execution instruction specifies a first flag register, the system copies the flag bits in the first flag register to a corresponding second flag register, and saves a result of each of the target instructions dependent upon the specified condition in the first flag register during execution of the conditional execution instruction.