Patents by Inventor Seshasayee Gaddamraja

Seshasayee Gaddamraja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9564569
    Abstract: A sensor-in-package device, a process for fabricating a hermetically-sealed sensor-in-package device, and a process for fabricating a hermetically-sealed sensor-in-package device with a pre-assembled hat that employ example techniques in accordance with the present disclosure are described herein. In an implementation, the sensor-in-package device includes a substrate; at least one thermopile, at least one photodetector, at least one light-emitting diode, an ultraviolet light sensor, and a pre-assembled hat disposed on the first side of the substrate, where the pre-assembled hat includes a body; a first lid; and a second lid; where the body, the substrate, and the first lid define a thermopile cavity that houses the at least one thermopile, and where the body, the substrate, and the second lid define an optical cavity that houses at least one of the at least one photodetector, the at least one light-emitting diode, or the ultraviolet light sensor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 7, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ken Wang, Jerome C. Bhat, Tian Tian, Seshasayee Ankireddi, Kumar Nagaranjan, Seshasayee Gaddamraja
  • Patent number: 9196608
    Abstract: Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 24, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sally Foong, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
  • Patent number: 9136258
    Abstract: An optical sensor device, system, and method are described that include a substrate, an electronic device disposed on the substrate, a molding layer, a lens, and a light-emitting diode (LED) package disposed on the substrate and at least partially over the sensor and molding layer. The LED package can include an LED substrate, an LED, a lens disposed on the LED, and electrical interconnections for coupling the LED to the substrate. In implementations, a process for fabricating the optical sensor device includes backgrinding a sensor die to a slim profile; attaching the sensor die onto a substrate; placing a molding layer on the sensor die; forming a lens on the molding layer; and placing an assembled light-emitting diode package on the substrate and at least partially over the sensor die and molding layer, where the assembled light-emitting diode package includes a 3D substrate.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ken Wang, Kumar Nagarajan, Seshasayee Gaddamraja
  • Patent number: 8901756
    Abstract: Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 2, 2014
    Assignee: Spansion LLC
    Inventors: Sally Foong, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
  • Publication number: 20140175613
    Abstract: Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: Spansion LLC
    Inventors: Sally FOONG, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
  • Publication number: 20090001599
    Abstract: Systems, methods, and/or devices that facilitate stacking dies in a multi-die stack using film over wire and attaching a die to a substrate are presented. Film over wire (FOW) techniques can be employed to facilitate stacking dies that are the same or similar in size such that the wires bonded onto the lower die can be embedded in film used to attach the two dies. FOW techniques can also be employed to embed a smaller die and wires attached thereto in film underneath a larger die stacked on top of the lower die such that the larger die can be supported by the film in areas where the larger die would otherwise overhang. Die attach film can be utilized to facilitate attaching a die to a substrate such that all areas between the die and substrate are filled thereby reducing or eliminating delamination.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Applicant: SPANSION LLC
    Inventors: Sally Foong, Tan Kiah Ling, Cheng Sim Kee, Seshasayee Gaddamraja, Yue Ho Foong