Abstract: A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.

Abstract: A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.

Abstract: An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided.

Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.

Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Abstract: Disclosed is an adaptive negative bit-line boost write assist technique in which coupling capacitance scales with the number of rows and thereby maintains a constant negative bit-line level. The change in the coupling capacitance in neighboring signals as the height increases is utilized. The change is utilized for negative bit-line voltage generation.

Abstract: A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

Abstract: An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense amplifiers. The sense amplifier control circuitry comprises reaction time tracking circuitry including at least one dummy sense amplifier configured to track reaction time of one or more of the output sense amplifiers, with the sense amplifier control signal being generated at least in part responsive to an output signal of the dummy sense amplifier.

Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.

Abstract: Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the access cycle and to apply the further voltage to a further word line during the first time interval portion of the access cycle and to apply the voltage to the further word line during the further time interval of the access cycle.

Abstract: Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the access cycle and to apply the further voltage to a further word line during the first time interval portion of the access cycle and to apply the voltage to the further word line during the further time interval of the access cycle.