Abstract: A wafer processing method of the present invention includes mounting a wafer part on a chuck table, loading the wafer part on the chuck table, spraying, by a spray arm module, a first processing solution onto the wafer part to process the wafer part, spraying, by the spray arm module, a second processing solution onto the wafer part to process the wafer part, drying the wafer part on the chuck table, and unloading the wafer part from the chuck table.

Abstract: A fluid discharging nozzle cleaning apparatus includes: a cup in which an inner space, an upper opening which is open to allow a fluid discharging nozzle to enter the inner space, and a lower opening through which a cleaning liquid is discharged from the inner space to an outside are formed; a cleaning liquid discharger configured to discharge the cleaning liquid to the fluid discharging nozzle in a state in which the fluid discharging nozzle is positioned in the inner space of the cup; and a drying gas discharger configured to discharge a drying gas for drying the fluid discharging nozzle after the discharge of the cleaning liquid ends.

Abstract: A wafer processing method of the present invention includes mounting a wafer part on a chuck table, loading the wafer part on the chuck table, spraying, by a spray arm module, a first processing solution onto the wafer part to process the wafer part, spraying, by the spray arm module, a second processing solution onto the wafer part to process the wafer part, drying the wafer part on the chuck table, and unloading the wafer part from the chuck table.

Abstract: A wafer processing method of the present invention includes mounting a wafer part on a chuck table, loading a ring cover unit on the chuck table to restrain the wafer part to the chuck table, spraying, by a spray suction arm module, a processing solution onto the wafer part and suctioning, by the spray suction arm module, foreign materials from the processing solution, unloading the ring cover unit from the chuck table, and spraying, by a spray arm module, a cleaning solution onto the wafer part to clean the wafer part.

Abstract: A wafer processing apparatus of the present invention includes a suction nozzle configured to suction sludge from a cup housing, a flow line connected to the suction nozzle such that the sludge and a chemical solution flow therein, a suction tank connected to the flow line such that the sludge and the chemical solution flow thereto, and an ejector installed on a flow line to generate suction pressure in the suction nozzle and the flow line.

Abstract: A wafer cleaning apparatus of the present invention includes a vacuum chuck unit on which a wafer is mounted, and an ultrasonic cleaning module configured to spray a cleaning solution onto the wafer and apply ultrasonic waves to the cleaning solution to ultrasonically vibrate the cleaning solution.

Abstract: A wafer cleaning apparatus of the present invention includes a vacuum chuck unit on which a wafer is mounted, a ring cover unit facing a retainer ring portion of the wafer, an expander module installed to move the ring cover unit and configured to press the retainer ring portion toward the vacuum chuck unit such that a gap between dies of the wafer widens, and a chucking module installed in the vacuum chuck unit to restrain the ring cover unit pressed by the expander module to the vacuum chuck unit.

Abstract: A wafer processing apparatus of the present invention includes a first chamber unit in which a first wafer part including a retainer ring portion and a plurality of sawn first dies is processed, a second chamber unit in which a second wafer part including a wafer part or a carrier substrate is processed, and a third chamber unit in which the first dies of the first wafer part processed in the first chamber unit and the second wafer part processed in the second chamber unit are stacked and pre-bonded.

Abstract: There are provided an electric double layer capacitor cell, an electric double layer capacitor package having the same, and methods of manufacturing the same. An electric double layer capacitor cell according to an aspect of the invention may include: a plurality of electric double layer capacitor unit cells stacked upon each other, wherein each of the plurality of electric double layer capacitor unit cells includes first and second current collectors having first and second lead terminal portions, respectively, first and second electrodes provided on the first and second current collectors, respectively, and a separator provided between the first and second electrodes, and the first and second electrode lead terminal portions each are combined into one to provide first and second bonding portions being connected to external terminals provided to apply electricity to the electric double layer capacitor unit cells.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.