Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: The present disclosure relates to a memory system capable of encrypting and storing data, and a memory controller. The memory controller may include a first interface configured to perform data Communication with a first external device, a second interface configured to generate a signal for controlling an operation of a second extern& device and transmit the signal; and a processor configured to receive, from the first external device, a data write command to write data to the second external device, encrypt the data by using one of a plurality of keys stored in a key area provided in the first external device in response to the data write command, and then control the encrypted data to be written to the second external device.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device, checking whether the interface device is in a predetermined mode for adjusting the one or more parameters, adjusting, upon determination that the interface device is in the predetermined mode, the one or more parameters associated with the clock signals of the interface device based on how much of the first buffer or the second buffer is filled with data, and performing the data transmission or reception based on the adjusted one or more parameters associated with the clock signals.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Abstract: Devices for performing communications are disclosed. In some implementations, a device includes: an upstream port for receiving data from or transmitting data to one or more external devices located on an upstream path through a link including a plurality of lanes; a lane margining controller coupled to the upstream port and for transmitting, via the upstream port, to the one or more external devices, a margin command for requesting a lane margining operation to acquire margin status information to indicate a margin of each of the plurality of lanes, and controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to be in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: A peripheral component interconnect express (PCIe) device includes a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host. Each function type may be a physical function type, a virtual function type, or a disable function type.

Abstract: A Peripheral Component Interconnect Express (PCIe) function includes an access identification information controller generating first access identification information for allowing an access to the PCIe function, and providing the first access identification information to an assigned system image to which the PCIe function has been assigned, the assigned system image being one of a plurality of system images, a data packet receiver receiving a data packet including target identification information indicating a target system image selected from the plurality of system images from the target system image, and an access allowance determiner determining whether or not to allow an access of the first target system image based on the access identification information and the target identification information.

Abstract: Devices for performing communications are disclosed. In some implementations, a device includes: an upstream port for receiving data from or transmitting data to one or more external devices located on an upstream path through a link including a plurality of lanes; a lane margining controller coupled to the upstream port and for transmitting, via the upstream port, to the one or more external devices, a margin command for requesting a lane margining operation to acquire margin status information to indicate a margin of each of the plurality of lanes, and controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to be in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

Abstract: A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device, checking whether the interface device is in a predetermined mode for adjusting the one or more parameters, adjusting, upon determination that the interface device is in the predetermined mode, the one or more parameters associated with the clock signals of the interface device based on how much of the first buffer or the second buffer is filled with data, and performing the data transmission or reception based on the adjusted one or more parameters associated with the clock signals.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: A photoacid generator represented by the following formula (1), a method for producing the photoacid generator, and a resist composition containing the photoacid generator are provided. wherein in the formula (1), Y, X, R1, R2, n1, n2 and A+ have the same meanings as defined in the detailed description of the invention. The photoacid generator can maintain an appropriate contact angle at the time of ArF liquid immersion lithography, can reduce defects occurring during liquid immersion lithography, and has excellent solubility in resist solvents and excellent compatibility with resins. Furthermore, the photoacid generator can be produced by an efficient and simple method using an epoxy compound that is industrially easily available.

Abstract: A sulfonium compound represented by the following formula (1), a photoacid generator containing the sulfonium compound, and a resist composition containing the photoacid generator are provided: wherein X represents an electron donor group; R1 and R2 each independently represent an alkyl group or the like; R4 to R6 each independently represent an alkyl group, or the like; R3 represents a cyclic alkenediyl group or the like; and ?A represents an anion. The sulfonium compound has a photon yield that is controllable by introducing different absorbers to the cation region in one molecule, can address the inconvenience of using a mixture of different photoacid generators when the sulfonium compound is applied as a photoacid generator, has excellent miscibility in a resist, and has enhanced resolution and line edge roughness.

Abstract: Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.