Abstract: A circuit for controlling an internal voltage of a semiconductor memory apparatus including a deep power down signal input unit, which receives a deep power down signal indicating that a deep power down mode is starting, and supplies the received signal to a level shifter; and one or more level shifters, each of which performs level shifting from a first voltage to a second voltage or sinks the second voltage to a ground voltage in response to the input of the deep power down signal.

Abstract: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference voltage level, a controller that generates an active control signal in response to a power-down signal and an active signal, and an active voltage generator that generates the DLL internal voltage of the reference voltage level in response to the active control signal. After the power-down mode is ended, the active voltage generator is additionally operated during a predetermined time when the DLL is initially enabled. It is therefore possible to generate stabilized DLL internal voltages.

Abstract: An internal voltage generation circuit of a semiconductor device is disclosed. The internal voltage generation circuit comprises a reference voltage generator for generating a reference voltage having different levels depending on different operation modes of the semiconductor device, an active voltage generator for generating an active internal voltage of a level based on the reference voltage, a standby voltage generator for generating a standby internal voltage of a level based on the reference voltage, and an active voltage generation controller for controlling the active voltage generator such that the active voltage generator outputs the active internal voltage in a specific period after completion of a self-refresh mode.

Abstract: Provided is directed to an apparatus and method of supplying power in a semiconductor memory device which supplies an external voltage of high level at the beginning operation which current consumption is rapidly increased and then supplies an internal voltage of a target level, but the external voltage is supplied for a longer time in case that the current consumption is increased more when plural pairs of bitlines are selected than when a pair of bitlines is selected, and thus the apparatus comprises the relatively small number of internal voltage generators and also it is capable of improving reliability of a circuit operation.

Abstract: A reference voltage generating circuit for outputting a reference voltage having a level varying depending on the operation mode of a semiconductor device is disclosed.

Abstract: An initialization signal generation circuit is provided which includes a voltage divider for dividing an external voltage, generating an enable signal, and outputting the enable signal to a first node, a controller including at least one fuse, and adjusting a voltage level of the enable signal according to a cutting of the at least one fuse, and a signal generator for generating an initialization signal of a semiconductor device in response to the enable signal of the first node.

Abstract: A circuit for controlling an internal voltage of a semiconductor memory apparatus including a deep power down signal input unit, which receives a deep power down signal indicating that a deep power down mode is starting, and supplies the received signal to a level shifter; and one or more level shifters, each of which performs level shifting from a first voltage to a second voltage or sinks the second voltage to a ground voltage in response to the input of the deep power down signal.

Abstract: An on die termination (ODT) mode transfer circuit, for use in a semiconductor memory device, including: a delay locked loop (DLL) for receiving an external clock signal in order to generate a DLL clock signal according to a power down mode and an active-standby mode; an ODT mode signal generation means for generating an ODT mode signal in response to the DLL clock signal and a clock enable signal; and an ODT control means for generating a termination resistor (RTT) signal in response to an ODT signal and the ODT mode signal.

Abstract: Provided is directed to an internal supply voltage generator for a delay locked loop circuit which can prevent a tAC for a next read command from being outputted with a delay, by blocking a supply voltage VDLL from a transient lowering regardless of a reacting speed of a VDLL supply voltage generator by means of maximizing a driving power of the VDLL supply voltage generator which generates the supply voltage VDLL of a delay locked loop during entering time from a power down period to a power up period. Furthermore, as the supply voltage VDLL is prevented from lowering without rising the reacting speed of the VDLL supply voltage generator, it is advantageous to prevent a distorting phenomenon of the supply voltage VDLL in response to a fast reacting speed of the VDLL supply voltage generator.

Abstract: An on die termination (ODT) mode transfer circuit, for use in a semiconductor memory device, including: a delay locked loop (DLL) for receiving an external clock signal in order to generate a DLL clock signal according to a power down mode and an active-standby mode; an ODT mode signal generation means for generating an ODT mode signal in response to the DLL clock signal and a clock enable signal; and an ODT control means for generating a termination resistor (RTT) signal in response to an ODT signal and the ODT mode signal.

Abstract: There is provided a semiconductor device using an ODT technology, which is capable of minimizing a delay of an RTT formation timing or a misalignment of RTT with respect to clock, which may occur in a conversion of ODT signal before and after a conversion of a power down mode into an active/standby mode.

Abstract: There is provided a semiconductor device using an ODT technology, which is capable of minimizing a delay of an RTT formation timing or a misalignment of RTT with respect to clock, which may occur in a conversion of ODT signal before and after a conversion of a power down mode into an active/standby mode.

Abstract: A charge pump circuit with improved pump efficiency and usable in a semiconductor memory device, includes a charge node, a pump capacitor for pumping charges of the charge node, a charge transfer transistor connected between the charge node and an output node so as to transfer the charges of the pumped charge node, a charging transistor for charging the charge node with a predetermined voltage, and a first transistor coupled to the charge node for preventing flow-back of charges from an output node to the charge node during a charging interval.

Abstract: A charge pump circuit with improved pump efficiency and usable in a semiconductor memory device, includes a charge node, a pump capacitor for pumping charges of the charge node, a charge transfer transistor connected between the charge node and an output node so as to transfer the charges of the pumped charge node, a charging transistor for charging the charge node with a predetermined voltage, and a first transistor coupled to the charge node for preventing flow-back of charges from an output node to the charge node during a charging interval.

Abstract: The pumping circuit for pumping the internal voltage supplied to a semiconductor device is disclosed, which is directed to comparing an internal voltage with previously set two reference voltages and differently varying a swing width of an output pulse from an oscillator in accordance with a result of the comparison. When there is a big difference between the internal voltage and a desired first reference voltage, the swing width of the output pulse from the oscillator is normally set, and when the internal voltage becomes the first reference voltage, the swing width of the ouput pulse from the oscillator is decreased, and when the swing width is decreased, the increasing width of the level of the internal voltage which is pumped and supplied to the semiconductor device is decreased, so that the over pumping of the internal voltage is prevented.