Abstract: Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.

Abstract: Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.

Abstract: This invention relates to a synchronous dynamic random access memory in a semiconductor memory device, and particularly to a SDRAM in which a user can program a two (2) bank option or a four (4) bank option using an external signal so that it is possible to select one or more banks. An input section receives an external signal, an operation mode section stores an output signal from the input section, and a bank transformation section selects one or more banks using an output signal from the operation mode memory section. When adapted to a SDRAM, it is possible to operate a circuit having banks of different number from each other using an identical design.

Abstract: A semiconductor memory device comprising a memory cell array for storing input data therein, a data output buffer for outputting the data stored in the memory cell array externally, an output terminal for transferring the output data from the data output buffer externally, a data input buffer for transferring the output data from the data output buffer to the memory cell array, a data register for temporarily storing the transferred data from the data input buffer, and a multiplexer connected among the memory cell array, the data register and the data output buffer, for selecting one of the data stored in the memory cell array and the data stored in the data register and transferring the selected data to the data output buffer. In the normal case, the multiplexer selects the data stored in the memory cell array and transfers the selected data to the data output buffer.

Abstract: A parallel test circuit that can perform the parallel test and data reading of the memory device at the same time. By using it, one can shorten the test time. The parallel test circuit of the present invention has several MOS transistors N1 to NK where several data Data1 to DataK selected from the memory cell are input into each gate and their drains are commonly connected to an input/output line. Also, it has several MOS transistors n1 to nk where Data1 to DataK which are complementary data of said Data1 to DataK are input into each gate and their drains are commonly connected to another input/output line. Finally, it has load transistors P1 and P2 used to pre-charge said input/output lines. During the normal reading operation, it switches on data line pairs that have been selected, and then reads their data. During the parallel test, it evaluates whether the data is erroneous according to the output voltage level of the input/output lines by inputting all the data at the same time.