Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A method of fabricating a MOSFET is disclosed.

Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A method of fabricating a MOSFET is disclosed.

Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.

Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.

Abstract: There is disclosed a method of manufacturing a semiconductor device capable of preventing a facet profile generated at the time when an epitaxial silicon layer is formed. In order to accomplish the above object, the method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a gate including a mask insulating film and a sidewall spacer insulating film on a silicon substrate; a second step of growing a first epitaxial silicon layer on the exposed silicon substrate; and a third step of selectively growing a second epitaxial silicon layer on a facet region, wherein a boundary layer (layer in which the flow of hydrogen gas is substantially 0) for the flow of hydrogen gas on the entire structure for which the second step is completed and wherein the temperature of the facet region formed at the edge portion on the gate side in the first epitaxial silicon layer is higher than the temperature of its neighboring first epitaxial silicon layer.

Abstract: A method for fabricating a semiconductor device by one masking process using selective epitaxial growth, comprising the steps of providing a first conductive silicon substrate having an active region and field regions thereon and having a formed pad oxide layer on the surface, forming a trench having a width including the active region and field regions at both sides of the active region by etching the pad oxide layer and silicon substrate, forming a spacer having a width similar to that of the field region at both sidewalls of the trench and exposing active region of the silicon substrate, forming a second conductive well on the exposed active region of the silicon substrate by growing an in-situ doped silicon epi layer to a height similar to a surface of the silicon substrate, depositing an oxide layer on the resultant structure to fill a gap between the spacer and the well and performing planarization of the oxide layer to expose a surface of the silicon substrate and to form isolation layers at both sides

Abstract: A method for fabricating a semiconductor device by one masking process using selective epitaxial growth, comprising the steps of providing a first conductive silicon substrate having an active region and field regions thereon and having a formed pad oxide layer on the surface, forming a trench having a width including the active region and field regions at both sides of the active region by etching the pad oxide layer and silicon substrate, forming a spacer having a width similar to that of the field region at both sidewalls of the trench and exposing active region of the silicon substrate, forming a second conductive well on the exposed active region of the silicon substrate by growing an in-situ doped silicon epi layer to a height similar to a surface of the silicon substrate, depositing an oxide layer on the resultant structure to fill a gap between the spacer and the well and performing planarization of the oxide layer to expose a surface of the silicon substrate and to form isolation layers at both sides

Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.

Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.

Abstract: During selective epitaxial growth processing using LPCVD equipment, a SiGe epitaxial layer and a Si epitaxial layer are sequentially formed so that lateral overgrowth that could occur in formation of only Si epitaxial layer can be effectively restricted. By adjusting Ge density, SiGe migration is induced at selective epitaxial growth temperatures for forming the conventional Si epitaxial layer. And, by utilizing the internal stress of SiGe and lattice mismatch between the SiGe epitaxial layer and the Si epitaxial layer, the lateral overgrowth is restricted. Furthermore, by hydrogen thermal processing, surface topology of the epitaxial layer is improved.