Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: Disclosed are an LCD device and a driving method thereof. The LCD device includes at least one source driving ICs configured to drive a plurality of data lines formed in a panel, a timing controller configured to generate a power control signal used to change a level of a driving voltage applied to the source driving ICs according to a pattern of an image output to the panel, and a driving voltage generator configured to generate a first driving voltage or a second driving voltage according to the power control signal to drive the source driving ICs. The first and second driving voltages have different levels.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

Abstract: Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first judgment circuit judges program pass of the main cells, and the second judgment circuit judges program pass of the flag cells by applying a more strict judgment reference than the first judgment circuit.

Abstract: In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: A method of programming a non-volatile memory that includes dumping first page data loaded to a cache latch to a first data latch and backing up the first page data to a second data latch.

Abstract: Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first judgment circuit judges program pass of the main cells, and the second judgment circuit judges program pass of the flag cells by applying a more strict judgment reference than the first judgment circuit.

Abstract: Discussed is a transflective liquid crystal display device, capable of improving luminance, the device including a liquid crystal display panel provided with first and second substrates, a plurality of pixel regions defined by a plurality of gate lines and data lines on the first substrate, a thin film transistor formed on each pixel region, a black matrix and a color filter layer formed on the second substrate, and a liquid crystal layer interposing between the first an second substrates, a first polarizer and a second polarizer disposed above and below the liquid crystal display panel, respectively, a backlight unit disposed below the second polarizer to emit light to the liquid crystal display panel, a selective reflection film disposed between the liquid crystal display panel and the second polarizer so as to reflect light incident from the exterior and transmit light emitted from the backlight unit, a first reflecting layer formed on at least one of the gate line and the data line of the liquid crystal d