Abstract: A security device for a digital computer system having a peripheral device and peripheral device controller, includes a security user input/output unit which displays the contents stored in the peripheral device and receives the information for the protection of the peripheral device, a security system controller which is connected to the security user input/output unit, and protects and controls the peripheral device, and a security controller which is connected to the security system controller, the peripheral device controller and the peripheral device, and protects the peripheral device from being controlled by the peripheral device controller to provide a security device operated under another operating system by using hardware, thereby allowing a computer system to interface with an input/output device or a file in a normal state while the security device protects the computer system.

Abstract: An apparatus for detecting an operating state of a cooling fan in a computer system protects the computer system from damage due to excessive heat by preventing further operation of the computer system when the cooling fan is operating in an abnormal condition. The apparatus includes a pulse generating circuit for generating pulses in accordance with the motion of a cooling fan while the cooling fan revolves. A per revolution pulse generating circuit generates a pulse signal for every revolution of the cooling fan in accordance with the pulse signals provided from the pulse generating circuit. A dividing counter circuit outputs pulse signals having a specified period set in accordance with incoming data and reference clock signals. A revolution state determining circuit sets a time period for checking the operating state of the cooling fan in accordance with the pulse signals provided from the dividing counter circuit.

Abstract: A cache line replacing apparatus for use in a computer system having a central processing unit (CPU), a main memory and a cache memory, in which a cache line information of a CPU/cache bus is written-back into the main memory, and desired cache line information is read from the main memory to a memory bus to transmit the read cache line information to the CPU/cache bus, the cache line replacing apparatus including a first storage unit in which write-back data of the CPU/cache bus is stored, a second storage unit in which data which is read from the main memory to the memory bus is stored, a register for increasing a count value thereof when data is stored in the second storage means and decreasing the count value when the data is read from the second storage means, and a multiplexer for selectively transmitting the data stored in the second storage means to the CPU/cache bus or transmitting the data of the memory bus to the CPU/cache bus, according to the count value of the register.