Patents by Inventor Seung-Hyun Lim

Seung-Hyun Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8659339
    Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wun-Ki Jung, Kwi-Sung Yoo, Min-Ho Kwon, Jae-Hong Kim, Seung-Hyun Lim, Yu-Jin Park
  • Publication number: 20140024189
    Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 23, 2014
    Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
  • Publication number: 20130270631
    Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 17, 2013
    Inventors: Bi-o KIM, Jin-tae NOH, Chang-woo SUN, Jae-young AHN, Seung-hyun LIM, Ki-hyun HWANG
  • Patent number: 8547461
    Abstract: An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wun-Ki Jung, Seung-Hyun Lim, Dong-Hun Lee, Kwi-Sung Yoo, Min-Ho Kwon, Chi-Ho Hwang
  • Publication number: 20130135503
    Abstract: An apparatus includes an operational amplifier circuit comprising at least one operational amplifier and a feedback circuit coupled between the output terminal and input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output of the first operational amplifier. The apparatus further includes a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 30, 2013
    Inventors: Yu Jin Park, Soon Hwa Kang, Min Ho Kwon, Jae Hong Kim, Kwi Sung Yoo, Seung Hyun Lim
  • Patent number: 8432471
    Abstract: A CMOS image sensor includes a photodiode, a switch configured to transfer a signal sensed by the photodiode to a sensing node, and a comparator electrically and directly connected to the sensing node and configured to compare the sensed signal of the sensing node and a ramp signal. Reset offset of the comparator is maintained at a constant offset voltage level during an initialization mode.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung hyun Lim, Jeong hwan Lee, Kun hee Cho, Gun Hee Han, Kwi Sung Yoo, Seog heon Ham
  • Publication number: 20130099090
    Abstract: A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 25, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: YU JIN PARK, KWI SUNG YOO, SEUNG HYUN LIM
  • Patent number: 8314457
    Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Kim, Sun-Il Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim
  • Patent number: 8269268
    Abstract: The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: September 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zong-liang Huo, In-seok Yeo, Seung-Hyun Lim, Kyong-hee Joo, Jun-kyu Yang
  • Publication number: 20120176501
    Abstract: An image sensor includes a pixel array including a plurality of pixels which are arranged in a matrix of a plurality of rows and columns and each of the plurality of pixels being configured to convert intensity of incident light into an electrical image signal; and an extended counting analog-to-digital converter configured to perform a first analog-to-digital conversion to provide a digital signal from an output signal of the pixel array, to obtain a residue using the output signal of the pixel array and the digital signal, and to perform a second analog-to-digital conversion using the residue.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 12, 2012
    Inventors: Kwi Sung Yoo, Min Ho Kwon, Wun-Ki Jung, Jin Ho Seo, Dong Hun Lee, Seung Hyun Lim, Jae Hong Kim
  • Publication number: 20120133800
    Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.
    Type: Application
    Filed: October 13, 2011
    Publication date: May 31, 2012
    Inventors: Wun-Ki Jung, Kwi-Sung Yoo, Min-Ho Kwon, Jae-Hong Kim, Seung-Hyun Lim, Yu-Jin Park
  • Publication number: 20120113286
    Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.
    Type: Application
    Filed: October 11, 2011
    Publication date: May 10, 2012
    Inventors: Seung-Hyun LIM, Kwi-Sung YOO, Kyoung-Min KOH, Yu-Jin PARK, Chi-Ho HWANG, Yong LIM
  • Publication number: 20120098990
    Abstract: An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 26, 2012
    Inventors: Wun-Ki JUNG, Seung-Hyun Lim, Dong-Hun Lee, Kwi-Sung Yoo, Min-Ho Kwon, Chi-Ho Hwang
  • Patent number: 8159589
    Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Lim, Gun Hee Han, Seog Heon Ham
  • Publication number: 20110198685
    Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Inventors: Hyun-Suk Kim, Sun-II Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim
  • Patent number: 7973357
    Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Kim, Sun-Il Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim
  • Publication number: 20110043676
    Abstract: A CMOS image sensor includes a photodiode, a switch configured to transfer a signal sensed by the photodiode to a sensing node, and a comparator electrically and directly connected to the sensing node and configured to compare the sensed signal of the sensing node and a ramp signal. Reset offset of the comparator is maintained at a constant offset voltage level during an initialization mode.
    Type: Application
    Filed: July 1, 2010
    Publication date: February 24, 2011
    Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seung hyun LIM, Jeong hwan LEE, Kun hee CHO, Gun Hee HAN, Kwi Sung YOO, Seog heon HAM
  • Patent number: 7651904
    Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: January 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyong-Hee Joo, Jin-Ho Park, In-Seok Yeo, Seung-Hyun Lim
  • Publication number: 20090321810
    Abstract: Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 31, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Kyung RYU, Byong-sun JU, Myoung-bum LEE, Seung-hyun LIM, Sung-hae LEE, Young-sun KIM
  • Patent number: 7629838
    Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: December 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hyun Lim, Jeong-Hwan Lee, Gun-Hee Han, Seog-Heon Ham