Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: A CMOS image sensor includes a photodiode, a switch configured to transfer a signal sensed by the photodiode to a sensing node, and a comparator electrically and directly connected to the sensing node and configured to compare the sensed signal of the sensing node and a ramp signal. Reset offset of the comparator is maintained at a constant offset voltage level during an initialization mode.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer.

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.

Abstract: In a method of forming a thin layer having a desired composition, a source gas is provided onto a substrate loaded in a chamber for a first time, and the source gas is chemisorbed onto the substrate. While the source gas is provided, a plasma is generated in the chamber for a second time to change the chemisorbed source gas into the thin layer having the desired composition. The thin layer may have a stoichiometrical composition or a non-stoichiometrical composition.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: An analog-to-digital converter (ADC) includes first and second circuits, a differential amplifier, a comparator and a digital-to-analog converter (DAC). The first circuit samples a reset voltage, amplifies the sampled reset voltage, and subtracts a first reference voltage from the amplified reset voltage to produce a first difference. The second circuit samples a signal voltage, amplifies the sampled signal voltage, and subtracts a second reference voltage from the amplified signal voltage to produce a second difference. The differential amplifier produces a third difference based a comparison of the first and second differences from the first and second circuits. The comparator compares an output of the differential amplifier with at least one predetermined comparison voltage and outputs a comparison result as a digital value. The DAC is connected to the first and second circuits and the comparator, and controls the first and second reference voltages in response to the digital value.

Abstract: A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.

Abstract: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.

Abstract: A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, the plurality of nano dots being formed from a second material having a second band gap energy lower than the first band gap energy.

Abstract: The invention is directed generally to a correlated double-sampling (CDS) circuit using a smaller number of capacitors than conventional circuits. In embodiments of the invention, a first portion of the CDS circuit uses just two capacitors to sample the reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage. A second portion of the CDS circuit uses just two capacitors to sample the signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage. Embodiments of the invention also provide a cyclic analog-to-digital converter (ADC) including the CDS circuit.

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract: A method of forming a carbon nanotube includes forming a cavity between a substrate and a first layer on the substrate. The cavity extends in a wiring pattern and includes a metal catalyst pattern in the cavity. The carbon nanotube is formed from the metal catalyst pattern and extends inside the cavity along the wiring pattern. Related methods and devices are also discussed.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.

Abstract: A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the tunnel insulating film having a quantum confinement film.