Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, the plurality of nano dots being formed from a second material having a second band gap energy lower than the first band gap energy.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region.

Abstract: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

Abstract: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

Abstract: Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.

Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

Abstract: A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the tunnel insulating film having a quantum confinement film.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region. Methods of forming single transistor floating body dynamic random access memory (DRAM) cells are also provided.

Abstract: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.

Abstract: A nonvolatile semiconductor memory device includes a substrate having a trench therein, a gate electrode in the trench, and a plurality of source/drain regions in the substrate adjacent the gate electrode. A pair of channel regions extends along sidewalls of the trench between respective pairs of adjacent source/drain regions. A charge trapping layer is between the gate electrode and the channel regions, and an insulation layer is between the charge trapping layer and the channel regions. Methods of forming nonvolatile semiconductor memory devices include forming a recess in a substrate, forming a first source/drain region beneath the recess, and forming a second source/drain region and a third source/drain region at an upper portion of the substrate on opposing sides of the recess and spaced apart from the first source/drain region. An insulation structure in the recess includes first and second insulation layers and a charge trapping layer between the first and the second insulation layers.

Abstract: A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.