Abstract: Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate electrode is formed on a portion of the surface extending opposite the body region and between the source and drain regions. A gate electrode insulating layer is also disposed between the gate electrode and the surface. To improve the transistor's withstand voltage capability by reducing field crowding, the gate electrode insulating layer is preferably formed to have a tapered thickness which increases in a direction from the source region to the drain region, and to reduce on-state resistance the drain region is formed in a self-aligned manner to the gate electrode.

Abstract: Methods of forming power semiconductor devices include the steps of forming an insulated gate electrode on a face of semiconductor substrate containing a body region of first conductivity type (e.g., P-type) therein extending to the face. Using the gate electrode as a mask, a step is then performed to oxidize the body region and substrate at the face to form a first oxide layer. Source and drain region dopants are then implanted through the first oxide layer and into the body region and substrate to define recessed source and drain regions of second conductivity type therein, respectively. The step of implanting source and drain region dopants may be preceded by the step of etching the first oxide layer using an etching mask which covers the gate electrode. The step of oxidizing the body region and substrate may also be preceded by the step of forming nitride spacers on sidewalls of the gate electrode and then also using the nitride spacers as a mask during the oxidation step.

Abstract: A method of forming an integrated circuit device includes the steps of forming a first insulating layer on an integrated circuit substrate, forming a first capacitor electrode on the insulating layer opposite the substrate, and forming a second insulating layer on the first capacitor electrode and on the insulating layer opposite the substrate. A contact hole is formed in the second insulating layer thus exposing a surface of the first capacitor electrode. In particular, the contact hole exposes an edge portion of the first capacitor electrode and extends beyond the edge portion of the first capacitor electrode. A capacitor dielectric layer is formed on the exposed portion of the first capacitor electrode wherein the capacitor dielectric layer extends beyond the edge portion of the first capacitor electrode. A second capacitor electrode is formed on the dielectric layer wherein the second capacitor electrode extends beyond the edge portion of the first capacitor electrode.

Abstract: A method of forming an integrated circuit device includes the steps of forming a first insulating layer on an integrated circuit substrate, forming a first capacitor electrode on the insulating layer opposite the substrate, and forming a second insulating layer on the first capacitor electrode and on the insulating layer opposite the substrate. A contact hole is formed in the second insulating layer thus exposing a surface of the first capacitor electrode. In particular, the contact hole exposes an edge portion of the first capacitor electrode and extends beyond the edge portion of the first capacitor electrode. A capacitor dielectric layer is formed on the exposed portion of the first capacitor electrode wherein the capacitor dielectric layer extends beyond the edge portion of the first capacitor electrode. A second capacitor electrode is formed on the dielectric layer wherein the second capacitor electrode extends beyond the edge portion of the first capacitor electrode.