Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

Abstract: A method of operating a memory device comprises receiving a first row address corresponding to a first word line in the first sub bank array and corresponding to a first word line in the second sub bank array, determining whether at least one of the first word lines has been replaced with a spare word line, (a) when neither of the first word lines has been replaced, receiving a first number of row addresses for refresh operations in order to refresh adjacent word lines to the first word lines, and (b) when at least one of the first word lines has been replaced with a spare word line, receiving a second number of row addresses for refresh operations in order to refresh adjacent word lines to any non-replaced first word and any spare word lines, wherein the second number is greater than the first number.

Abstract: A method of operating a memory device comprises receiving a first row address corresponding to a first word line in the first sub bank array and corresponding to a first word line in the second sub bank array, determining whether at least one of the first word lines has been replaced with a spare word line, (a) when neither of the first word lines has been replaced, receiving a first number of row addresses for refresh operations in order to refresh adjacent word lines to the first word lines, and (b) when at least one of the first word lines has been replaced with a spare word line, receiving a second number of row addresses for refresh operations in order to refresh adjacent word lines to any non-replaced first word and any spare word lines, wherein the second number is greater than the first number.

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract: An automatic probe exchange system for a scanning probe microscope (SPM) exchanges probes between a probe mount on the SPM and a probe mount on a probe tray based on differential magnetic force. When the magnetic force on the SPM side is greater, the probe is attached to the probe mount on the SPM. When the magnetic force on the probe tray side is greater, the probe is attached to the probe mount on the probe tray. The magnetic force on the probe tray side is varied by moving the magnets that generate the magnetic force on the probe tray side closer to or further from the probe.

Abstract: A method of transforming a G-code type part program into a STEP-NC language type part program is provided and more particularly, a method is provided for enabling a G-code type part program mainly used in the field to be easily applied to a STEP-NC controller without a troublesome correction. A STEP-NC language type part program is automatically created, which is composed of machining operation information, manufacturing feature information, machining strategy information and the like, through a process of analyzing G-codes from the G-code type part program and tool information. A method of transforming a G-code into a STEP-NC part program includes receiving a G-code part program, tools and a numerical controller; creating G-code block information, and partitioning the entire part program on a workingstep basis. The method further includes creating machining strategy information and creating the STEP-NC part program by arranging the machining workingsteps.

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract: The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single electron transistor operating at room temperature, in which a quantum dot or a silicide quantum dot using a nanostructure is formed and a gate is positioned on the quantum dot so as to minimize influence on a tunneling barrier and achieve improved effectiveness in electric potential control for the quantum dot and operating efficiency of the transistor, and a manufacturing method for same.

Abstract: Provided is a scanning probe microscope (SPM), a probe of which can be automatically replaced and the replacement probe can be attached onto an exact position. The SPM includes a first scanner that has a carrier holder, and changes a position of the carrier holder in a straight line; a second scanner changing a position of a sample on a plane; and a tray being able to store a spare carrier and a spare probe attached to the spare carrier. The carrier holder includes a plurality of protrusions.

Abstract: An automatic probe exchange system for a scanning probe microscope (SPM) exchanges probes between a probe mount on the SPM and a probe mount on a probe tray based on differential magnetic force. When the magnetic force on the SPM side is greater, the probe is attached to the probe mount on the SPM. When the magnetic force on the probe tray side is greater, the probe is attached to the probe mount on the probe tray. The magnetic force on the probe tray side is varied by moving the magnets that generate the magnetic force on the probe tray side closer to or further from the probe.

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.