Abstract: A power supply apparatus and a power supply method are disclosed. The power supply apparatus may include an internal power supply including a first voltage generator configured to generate a first voltage based on a pulse width modulation control signal, a charge pump configured to receive the first voltage and generate a second voltage, and an inrush current controller configured to be connected between the charge pump and the internal power supply and configured to generate the pulse width modulation control signal based on a target signal and a selection reference voltage.

Abstract: The present invention relates to an anti-glare coating composition for preparation of anti-glare films having good anti-fingerprint properties as well as improved contrast ratio and image definition. More specifically, the coating composition comprises organic or inorganic particles, a photocurable resin, a photoinitiator, and a compound including an olefin oxide repeating unit.

Abstract: A display driving circuit includes a semiconductor die, a logic control unit, a gray-scale voltage generation unit and a driving unit. The logic control unit is on a central region of the semiconductor die, and is configured to control the display driving circuit based on a control signal. The gray-scale voltage generation unit is on an edge region of the semiconductor die, and is configured to generate a plurality of gray-scale voltages based on an input voltage. The driving unit is on a region of the semiconductor die between the logic control unit and the gray-scale voltage generation unit, and is configured to generate a plurality of driving voltages based on the plurality of gray-scale voltages and input data.

Abstract: In a liquid crystal display (LCD) panel driver with a self-masking function using a power-on reset signal, and in a method of driving the same, the LCD panel driver includes a power-on reset signal generation unit that generates a power-on reset signal in response to a supply voltage applied to a LCD panel; a latch unit that receives a start pulse signal instructing that source lines of the LCD panel be driven and generates first and second set signals for setting an initial value of an output signal of a flip-flop to be in a predetermined default logic level, in response to the power-on reset signal; and a counter unit that generates a start pulse masking signal by masking at least one pulse of the start pulse signal in response to the first and second set signals and the start pulse signal.

Abstract: A power supply apparatus and a power supply method are disclosed. The power supply apparatus may include an internal power supply including a first voltage generator configured to generate a first voltage based on a pulse width modulation control signal, a charge pump configured to receive the first voltage and generate a second voltage, and an inrush current controller configured to be connected between the charge pump and the internal power supply and configured to generate the pulse width modulation control signal based on a target signal and a selection reference voltage.

Abstract: A source driver includes a hold memory block, a pre-decoding block, a level shifting block and digital-to-analog (DAC) block. The hold memory block stores digital image data. The pre-decoding block generates a data code that includes at least one bit having a first logic level based on the digital image data and generates a plurality of enable signals based on the data code. The level shifting block performs level shifting of the data code based on the enable signals. The DAC block outputs a grayscale voltage that is selected based on the level shifted data code output from the level shifting block. A source driver module and a display device include a plurality of the source drivers.

Abstract: A driver integrated circuit (IC) for a liquid crystal display (LCD) has a double column structure. The driver IC includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores first and second group channel data in response to a clock signal generated by the first shift register unit. The first decoder receives the first group channel data and outputs gamma voltages corresponding to the first group channel data. The second decoder receives the second group channel data and outputs gamma voltages corresponding to the second group channel data. The first and second output buffers are aligned along a long edge of the driver IC and buffer the corresponding gamma voltages to drive corresponding channels. The first shift register unit and the first data latch unit are shared by upper and lower blocks to process the first and second group channel data together.

Abstract: A data line driver having a double column architecture includes a first driver cell including a first decoder, the first driver cell being connected to a first data line, and a second driver cell including a second decoder adjacent to the first decoder, the second driver cell being connected to a second data line.

Abstract: In a liquid crystal display (LCD) panel driver with a self-masking function using a power-on reset signal, and in a method of driving the same, the LCD panel driver includes a power-on reset signal generation unit that generates a power-on reset signal in response to a supply voltage applied to a LCD panel; a latch unit that receives a start pulse signal instructing that source lines of the LCD panel be driven and generates first and second set signals for setting an initial value of an output signal of a flip-flop to be in a predetermined default logic level, in response to the power-on reset signal; and a counter unit that generates a start pulse masking signal by masking at least one pulse of the start pulse signal in response to the first and second set signals and the start pulse signal.

Abstract: A source driver includes a hold memory block, a pre-decoding block, a level shifting block and digital-to-analog (DAG) block. The hold memory block stores digital image data. The pre-decoding block generates a data code that includes at least one bit having a first logic level based on the digital image data and generates a plurality of enable signals based on the data code. The level shifting block performs level shifting of the data code based on the enable signals. The DAC block outputs a grayscale voltage that is selected based on the level shifted data code output from the level shifting block. A source driver module and a display device include a plurality of the source drivers.

Abstract: An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output node to a control voltage in response to the control signal and a bias voltage. The output unit may maintain the first output signal between a given voltage and the control voltage based on the pull signal and the bias voltage.

Abstract: A driver integrated circuit (IC) for a liquid crystal display (LCD) has a double column structure. The driver IC includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores first and second group channel data in response to a clock signal generated by the first shift register unit. The first decoder receives the first group channel data and outputs gamma voltages corresponding to the first group channel data. The second decoder receives the second group channel data and outputs gamma voltages corresponding to the second group channel data. The first and second output buffers are aligned along a long edge of the driver IC and buffer the corresponding gamma voltages to drive corresponding channels. The first shift register unit and the first data latch unit are shared by upper and lower blocks to process the first and second group channel data together.

Abstract: Provided is a slew rate adjusting circuit, a source driver, a source driver module and a display device. The slew rate adjusting circuit may output a buffered signal, in response to an input signal input to an Mth stage shift register, where M is a natural number less than N, from a last stage of the N stage cascade shift register and a reference voltage output from a reference voltage generator, a slew rate of the buffered signal depending on a level of the reference voltage. The source driver may include an N stage cascade shift register, a reference voltage generator, a slew rate adjusting circuit, and/or a latch. The N stage cascade shift register may sequentially shift a start pulse driving the source driver in response to a clock signal. The reference voltage generator may generate a reference voltage.

Abstract: An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output node to a control voltage in response to the control signal and a bias voltage. The output unit may maintain the first output signal between a given voltage and the control voltage based on the pull signal and the bias voltage.