Patents by Inventor Seung-Mo HA
Seung-Mo HA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984448Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.Type: GrantFiled: October 25, 2021Date of Patent: May 14, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Bok Young Lee, Young Mook Oh, Hyung Goo Lee, Hae Geon Jung, Seung Mo Ha
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Publication number: 20240047521Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 11830911Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: February 1, 2023Date of Patent: November 28, 2023Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20230178595Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Patent number: 11610966Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: GrantFiled: November 25, 2019Date of Patent: March 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Patent number: 11575002Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: March 25, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Patent number: 11515390Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: GrantFiled: August 14, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Publication number: 20220231015Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.Type: ApplicationFiled: October 25, 2021Publication date: July 21, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Bok Young LEE, Young Mook OH, Hyung Goo LEE, Hae Geon JUNG, Seung Mo HA
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Publication number: 20220189970Abstract: A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.Type: ApplicationFiled: August 3, 2021Publication date: June 16, 2022Inventors: Haegeon JUNG, Taeyong KWON, Kwang-Yong YANG, Youngmook OH, Bokyoung LEE, Seung Mo HA, Hyunggoo LEE
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Publication number: 20210233995Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: March 25, 2021Publication date: July 29, 2021Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 10964782Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: December 16, 2019Date of Patent: March 30, 2021Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20200373387Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Inventors: Jung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
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Patent number: 10629604Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: GrantFiled: March 12, 2019Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-hee Bai, Myeong-cheol Kim, Kwan-heum Lee, Do-hyoung Kim, Jin-wook Lee, Seung-mo Ha, Dong-Hoon Khang
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Publication number: 20200119143Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 10622444Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: GrantFiled: September 7, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
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Patent number: 10622256Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.Type: GrantFiled: March 28, 2016Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin Mun, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Dong-Seok Lee, Yong-Joon Choi, Seung-Mo Ha, Do-Hyoung Kim
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Publication number: 20200091286Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Jung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
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Patent number: 10529801Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: March 23, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Patent number: 10411119Abstract: A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.Type: GrantFiled: April 7, 2016Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwan Lee, Sangsu Kim, Sanghyuk Hong, Seung Mo Ha
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Publication number: 20190214394Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Keun-hee BAI, Myeong-cheol KIM, Kwan-heum LEE, Do-hyoung KIM, Jin-wook LEE, Seung-mo HA, Dong-Hoon KHANG