Patents by Inventor Seung Yeop KOOK
Seung Yeop KOOK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230268266Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer, and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. At least a portion of a first wall of a first trench of the first insulating layer and at least a portion of a second wall of a second trench of the second insulating layer overlap each other vertically.Type: ApplicationFiled: March 20, 2023Publication date: August 24, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 11699650Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.Type: GrantFiled: January 18, 2021Date of Patent: July 11, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alamgir M. Arif, Sunil K. Singh, Dewei Xu, Seung-Yeop Kook, Roderick A. Augur
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Patent number: 11626364Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: December 7, 2020Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20220230955Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.Type: ApplicationFiled: January 18, 2021Publication date: July 21, 2022Inventors: Alamgir M. Arif, Sunil K. Singh, Dewei Xu, Seung-Yeop Kook, Roderick A. Augur
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Patent number: 11348867Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.Type: GrantFiled: November 5, 2020Date of Patent: May 31, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Dewei Xu, Sunil K. Singh, Seung-Yeop Kook, Roderick A. Augur
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Publication number: 20220139819Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Inventors: Dewei Xu, Sunil K. Singh, Seung-Yeop Kook, Roderick A. Augur
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Patent number: 11107880Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.Type: GrantFiled: May 10, 2019Date of Patent: August 31, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Dewei Xu, Sunil K. Singh, Siva R. Dangeti, Seung-Yeop Kook
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Publication number: 20210118791Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 10861784Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: May 27, 2020Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20200357880Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Dewei Xu, Sunil K. Singh, Siva R. Dangeti, Seung-Yeop Kook
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Publication number: 20200294904Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: May 27, 2020Publication date: September 17, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho KIM, Ji Hoon KIM, Ha Young AHN, Shang Hoon SEO, Seung Yeop KOOK, Sung Won JEONG
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Patent number: 10701806Abstract: A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.Type: GrantFiled: September 30, 2019Date of Patent: June 30, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong-Ho Baek, Jung-Hyun Cho, Seung-Yeop Kook
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Patent number: 10679933Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: October 10, 2019Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20200043842Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: October 10, 2019Publication date: February 6, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho KIM, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20200029435Abstract: A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong-Ho BAEK, Jung-Hyun CHO, Seung-Yeop KOOK
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Patent number: 10477683Abstract: A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.Type: GrantFiled: January 6, 2017Date of Patent: November 12, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong-Ho Baek, Jung-Hyun Cho, Seung-Yeop Kook
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Patent number: 10461008Abstract: An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.Type: GrantFiled: July 8, 2016Date of Patent: October 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Won Jeong, Ji Hoon Kim, Sun Ho Kim, Shang Hoon Seo, Seung Yeop Kook, Christian Romero
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Patent number: 10446481Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: July 18, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 10388614Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.Type: GrantFiled: March 6, 2018Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hyun Lee, Kyoung Moo Harr, Seung Yeop Kook, Ji Hoon Kim, Young Gwan Ko
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Patent number: 10270948Abstract: A substrate for a camera module includes: a first substrate; an image sensor installed on the first substrate and a memory chip installed to be embedded in the first substrate. The first substrate includes a soft substrate portion disposed at a central portion of the first substrate, and a hard substrate portion formed on upper and lower portions of the soft substrate portion, and at least a portion of the memory chip is disposed in an installation hole formed in the soft substrate portion.Type: GrantFiled: December 6, 2016Date of Patent: April 23, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Eun Lee, Jin Seon Park, Yul Kyo Chung, Chul Choi, Dae Young Jung, Seung Yeop Kook